/// Notes  and Demos for LSU EE 4702-1 Spring 2001

//  Synthesis Basics

//  Sources: Ci:  Ciletti, Modeling, synthesis, and rapid prototyping
//                         with the Verilog HDL
//           Leo: Exemplar Logic (Mentor Graphics),
//                         LeonardoSpectrum HDL Synthesis Manual, October 2000

/// Contents

// Ummm...


/// Design Flow

//  Covered So Far
//
//  1. Code Synthesizable Module 
//  2. Code Testbench (not optional)
//  3. Verify Module

//  New Steps  (Steps 4-6 Covered in Class)
//
//  4. Synthesize to RTL Description.      Output: Verilog (plus other format)
//  5. Synthesize to Technology (Mapping)  Output: Verilog (plus other format)
//  6. Verify Synthesized Verilog (Check for synthesis inaccuracies)
//  7. Place and Route


 /// Synthesize to RTL

//  Synthesis program creates a structural model of behavioral description.
//
//    Infer registers.
//      Determine which reg's are really registers ...
//      ... and when and how they are clocked.
//    Infer standard modules. (Integer adder, incrementer, memory, etc.)


 /// Synthesize to Technology (Technology Mapping)
//
//   Replaces generic gates (and, or) with technology specific gates,
//     (AN2X0, OR3X1).
//   Replaces standard modules with technology-optimized versions.
//   Optimizes logic. (Minimizes number of gates or length of path.)
//   

 /// Verify
//
//   Current synthesis programs inexact, output must be verified.


/// Terminology

 /// Infer

//   To determine what type of hardware to use for a fragment of
//   behavioral code, performed in the synthesize-to-RTL step of
//   synthesis.  Synthesis programs infer registers from behavioral
//   assignments (see description of forms below), arithmetic units
//   from arithmetic operators (obviously not a difficult thing to
//   infer), RAMs from certain usage of memories (reg arrays), etc.
//   Inference capabilities vary by synthesis program.

//   The inference step of turn-of-the-century synthesis programs
//   frequently generates hardware which is different than the
//   behavioral description they read, which is why the RTL generated
//   in the inference or later steps must be verified.

 /// Optimization [Of a Hardware Description]

//   The transformation of a design to one which uses fewer gates and
//   has a shorter critical path.  Synthesis programs can be directed
//   to primarily minimize the number of gates or to minimize the
//   critical path.  Timing constraints and other criteria can usually
//   be specified. (For example, the delay from input A to output X
//   shall be less than 12 ns.)  The term "optimization" is a rarely
//   achieved goal. "Best-effort minimization" more accurately
//   describes the process but no vendor seems willing to use such a
//   term. :-)

 /// Place and Route (P&R)

//   Usually the last synthesis step before tape-out.  Components are
//   assigned a physical location (placed) and connections between
//   components are determined (they are routed).

 /// Register Transfer Language (RTL)
//
//   (1) The output of the first stage of synthesis, in which
//   registers and other hardware have been inferred.

//   (2) A form of a description (also called a descriptive form) in a
//   hardware description language (such as Verilog) where registers
//   are explicitly specified.

//   (3) A hardware description language in which registers
//   are always explicitly specified. (Not Verilog or VHDL.)

 /// Tape-out

//   The last synthesis step in which the design database (files) are
//   written to tape (historically), to be sent to a silicon foundry
//   (fab) for fabrication.  Tape-out with some technology targets,
//   such as FPGAs, means writing out the data file that is to be
//   downloaded into an FPGA.

 /// Technology Mapping

//   Converting a hardware description using generic gates and modules
//   (such as adders and RAMs) to one using a set of gates and modules
//   specific to a design target.  For example, a two-input and gate
//   (a generic gate) might be mapped to a medium fan-out three-input
//   and gate in an ASIC's part library, with the third input tied
//   to logic 1.  A medium fanout gate being chosen because of the
//   number of gates to which the and gate connects.
//
//   Technology mapping is usually followed by optimization.

 /// Technology Target

//   The type of part to be fabricated or programmed.  Examples
//   include ASICs, gate arrays, PLAs, and FPGAs.

 /// Timing Verification

//   Verification of the design produced in the technology mapping
//   or place-and-out steps of synthesis.  Synthesis programs
//   can write HDL descriptions of the hardware they synthesized
//   that contain timing information based on the actual technology
//   gates used, the load those gates have to drive, etc.  



/// Three Synthesizable Verilog Forms

// Description is for Leonardo Spectrum v2000.1

// Leonardo can synthesize behavioral code if it is in one of 3 forms:

// Form 1:  Combinational / Level-Triggered
// Form 2:  Edge Triggered
// Form 3:  Implicit State Machine

// Each always block (within a module) can be in a different form.

// The form determines how registers are inferred.

 /// Summary of Forms
//
//  Form 1: Combinational / Level Triggered
//
//    Describes combinational logic.
//    Describes level-triggered registers.
//
//  Form 2: Edge Triggered
//
//    Describes registers clocked on the edge of a single signal.
//    Registers can also be written with constants using an asynchronous trigger.
//
//  Form 3: Implicit State Machine
//
//    Describes a state machine synchronized to a clock.
//
//
 ///  Caution
//
//    Code which is not in one of these forms may:
//
//      Cause synthesis to stop with a helpful error message.
//
//      Cause the synthesis program to issue a warning message but
//      continue to synthesize.  The synthesized description will
//      function differently than the Verilog code read by the
//      synthesizer.  This is why one must simulate the synthesized
//      code.
//
//      Be processed by the synthesizer without even a warning.  The
//      synthesized description will function differently than the
//      Verilog code read by the synthesizer.  Just think of the
//      "back in my day" stories you can tell your grandchildren
//      if they become EEs!

// Each form covered in a different set of notes.

/// Common to All Forms

 /// Assignment

//  A register can be assigned multiple times in an always block,
//  but the same register cannot be assigned in different always blocks.

// To be finished later....