// Solution to LSU EE 4701 Spring 2000 HW 5. `ifdef ALU module alu(res,err,a,b,op); input a, b, op; output res, err; parameter op_add = 0, // Addition. op_sub = 1, // Subtraction op_and = 2; // Bitwise and. wire [7:0] a, b; wire [2:0] op; reg [7:0] res; reg err; // exemplar full_case always @( a or b or op ) case( op ) op_add: {err,res} = a + b; op_sub: {err,res} = a - b; op_and: begin err = 0; res = a & b; end endcase // case( op ) endmodule // alu `endif module latch_thing(w,x,y,z,a,b,c,d,r,clk); input a, b, c, d, r, clk; output w, x, y, z; reg w, x, y, z; wire a, b, c, d, r, clk; always @( negedge clk or posedge r ) if( r ) w = 0; else w = d; always @( posedge clk or posedge r ) if( r ) y = 0; else y = a; always @( clk or c or r or d or b ) if( r ) z = 0; else if( clk && d == b ) z = c; wire deqb = d == a && clk; always @( posedge clk or posedge r or posedge deqb ) if( r ) x = 0; else if( deqb ) x = 1; else if( a ) x = b; endmodule // latch_thing