// Verilog code for solution to LSU EE 4702-1 Spring 2000 HW 1

// Name:

// Instructions:

// Do not rename the modules in this file.  Additional ones may
// be added.

////////////////////////////////////////////////////////////////////////////////
// Module names for Problem 1.

module number_detect_es(found,number);
   
endmodule // number_detect_es


module number_detect_is(found,number);
   
endmodule // number_detect_is

////////////////////////////////////////////////////////////////////////////////
// Module name for Problem 2.

module test_number_detect();
   
endmodule // test_nd


////////////////////////////////////////////////////////////////////////////////
// Code for Problem 3


module pos_edge_trigger(o,i);
   input i;
   output o;
   wire   noti;
   wire   preout;

   assign o = preout;

   not (noti,i);
   and (preout,i,noti);

endmodule // pos_edge_trigger


// Test bench for problem 3 solution.
// Already written!


module test_pos_edge();
   reg i;
   wire o;

   pos_edge_trigger et(o,i);

   initial
     begin
        i=0;
        #10;
        i=1;
        #1;
        i=0;
        #5;
        i=1;
        #2;
        i=0;
        #7;
        i=1;
        #9;
        i=0;
        #5;
     end
   
endmodule