The number of electrical wires (pins) leading into or out of an IC chip (see photo on left) is much smaller than the number of wires within the chip or on the printed circuit board outside the chip. This wiring bottleneck at the periphery of a chip is called the pin limitation. One function affected by pin limitation is that of externally selecting parts within a chip for special treatment. A chip could have a large number of such candidates for special treatment, requiring a large number of internal wires for selecting them. However, only a small number of pins is available for that purpose. A hardware module for this problem that expands inputs from a small number of pins to outputs at a large number of internal wires is called a decoder.
This “selection” problem is of particular interest in a class of chips called field-programmable gate arrays (FPGAs) that allows parts of the chip to be reconfigured (altered in structure and functionality) at run-time (while other parts of the chip are operating). This requires individual sections of the chip to be selected for reconfiguration.
Ramachandran Vaidyanathan (left), associate professor in the Department of Electrical and Computer Engineering, is researching a novel approach to solve the selection problem. He has designed a class of inexpensive decoders that can be configured to suit the particular selection problem at hand. Traditional decoders are either inexpensive, but inflexible or overly flexible and expensive. The new decoder occupies a middle ground delivering considerable flexibility at a small cost. It could add to the flexibility of FPGAs by reducing configuration time and opening new possibilities in ”reconfigurable computing.“ A patent for this technology is pending.
Given that most modern chips are, to some degree, pin-limited, and the widespread use of FPGAs, particularly in embedded systems, Vaidyanathan's results could impact many areas, ranging from consumer electronics, to satellites.