Research

Sponsors

  • National Science Foundation (NSF)
  • Department of Energy (DOE)
  • Oak Ridge Associated Universities (ORAU)
  • NASA / Louisiana Space Consortium
  • Louisiana Board of Regents
  • Chevron Innovative Research Support (CIRS) Fund
  • Louisiana State University

Publications

Refereed Conference Papers:

  • S. Chen, L. Peng, and S. Irving, “Accelerating GPU Hardware Transactional Memory with Snapshot Isolation,” In Proceedings of The ACM/IEEE 44th International Symposium on Computer Architecture (ISCA), Toronto, ON, Canada, Jun. 2017. (pdf). (Acceptance rate: 54/322 = 16.8%)
  • X. Xiang, W. Shi, S. Ghose, L. Peng, O. Mutlu, and N.-F. Tzeng, “Carpool: A Bufferless NoC with Adaptive Multicast and Hotspot Alleviation,” In Proceedings of the 31st ACM International Conference on Supercomputing (ICS), Chicago, IL, Jun. 2017.  (pdf) (Acceptance rate: 28/177 = 15.8%).

  • Z. Zhao, X. Chen, A. Srivastava, L. Peng, and S. P. Mohanty, “Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, Jul. 2017.  (pdf).
  • M. Fahad, Z. Zhao, A. Srivastava, and L. Peng, “Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design,” In Proceedings of The IEEE International Symposium on Nanoelectronic and Information Systems, Gwalior, India, Dec. 2016. (pdf).
  • Z. Zhao, A. Srivastava, L. Peng, and S. Mohanty, “A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic,” In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, Jul. 2016. (pdf).
  • S. Chen and L. Peng, “Efficient GPU Hardware Transactional Memory through Early Conflict Resolution,” In Proceedings of the 22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA), Barcelona, Spain, Mar. 2016. (pdf). (Acceptance rate: 53/240 = 22%)
  • Z. Zhao, A. Srivastava, L. Peng, S.-M. Chen, and S. Mohanty, “Circuit Implementation of Switchable Pins in Chip Multiprocessor,” In Proceedings of The IEEE International Symposium on Nanoelectronic and Information Systems, Inodre, India, Dec. 2015. (pdf)
  • B. Li, S.-M. Chen, and L. Peng, “Precise Computer Performance Comparisons Via Statistical Resampling Methods,” In Proceedings of The 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, PA. Mar. 2015. (pdf)
  • Y. Zhang, L. Zhao, R. Illikkal, R. Iyer, A. Herdrich,  and L. Peng, “QoS Management on Heterogeneous Architecture for Parallel Applications,” In Proceedings of The 32nd IEEE International Conference on Computer Design (ICCD), Seoul, Korea, Oct. 2014. (pdf)
  • Y. Zhang, S. Chen, L. Peng, and S.-M. Chen, “Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity,” In Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, Jul. 2014. (pdf)
  • S.-M. Chen, Y. Hu, Y. Zhang, L. Peng, J. Ardonne, S. Irving, and A. Srivastava, “Increasing Off-Chip Bandwidth in Multi-Core Processors with Switchable Pins,” In Proceedings of The ACM/IEEE 41st International Symposium on Computer Architecture (ISCA),  Minneapolis, MN, Jun. 2014. (Acceptance rate: 46/258 = 18%) (pdf).
  • S. Chen, G. Bronevetsky , B. Li, M. Casas, and L. Peng, “Evaluating Application Resilience with XRay,” In the 10th Workshop on Silicon Errors in Logic – System Effects (SELSE), Stanford University, CA, Apr. 2014. (pdf)
  • Y. Zhang, L. Duan, B. Li, L. Peng, and S. Sadagopan, “Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors,” In Proceedings of The 15th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2014. (pdf).
  • S.-M. Chen, Y. Hu, and L. Peng, “Optimization of Electricity and Server Maintenance Costs in Hybrid Cooling Data Centers,” In Proceedings of  The 6th IEEE  International Conference on Cloud Computing (CLOUD), Santa Clara, CA, Jun. 2013. (pdf).
  • Y. Zhang, L. Peng, X. Fu, and Y. Hu, “Lighting the Dark Silicon by Exploiting Heterogeneity on Future Processors,” In Proceedings of the 50th ACM/IEEE Annual Design Automation Conference (DAC), Austin, TX, Jun. 2013.  (Acceptance rate: 162/747 = 22%) (pdf).
  • Y. Hu, S.-M. Chen, L. Peng, E. Song, and J.-W. Choi, “Effective Thermal Control Techniques for Liquid-Cooled 3D Multi-Core Processors,” In Proceedings of The 14th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2013. (pdf)
  • S. Chen, L. Peng, G. Bronevetsky, and M. Casas‐Guix, “Library‐based Algorithmic Fault Tolerance for Scientific Applications,” In poster session of the 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). (pdf)
  • Y. Zhang, L. Duan, B. Li and L. Peng, “Optimal Microarchitectural Design Configuration Selection for Processor Hard-Error Reliability,” In Proceedings of The 13th IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2012. (pdf)
  • Y. Zhang, L. Peng, B. Li, J.-K. Peir and J. Chen, “Architecture Comparisons between NVidia and ATI GPUs: Computation Parallelism and Data Communications,” In Proceedings of The 2011 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, Nov. 2011. (pdf)
  • L. Duan, L. Peng and B. Li, “Two-Level Soft Error Vulnerability Prediction on SMT/CMP Architectures,” (extended abstract), In Proceedings of The 2011 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, Nov. 2011. (pdf)
  • J. Chen, B. Li, Y. Zhang, L. Peng and J.-K. Peir, “Tree Structured Analysis on GPU Power Study,” In Proceedings of The 29th IEEE International Conference on Computer Design (ICCD), Amherst, MA, Oct. 2011. (pdf)
  • Y. Zhang, Y. Hu, B. Li and L. Peng, “Performance and Power Analysis of ATI GPU: A Statistical Approach”, In Proceedings of The 6th IEEE International Conference on Networking, Architecture, and Storage (NAS), Dalian, China, Jul. 2011. (pdf)
  • J. Chen, B. Li, Y. Zhang, L. Peng and J.-K. Peir, “Statistical GPU Power Analysis Using Tree-based Methods”, In Proceedings of the Green Computing Conference and Workshops (IGCC), Orlando, FL, Jul. 2011. (pdf)
  • Y. Hu, D. Koppelman, and L. Peng, “Penalty-Sensitive L-TAGE Predictor,” in Proceedings of the 2nd JILP Workshop on Computer Architecture Competitions (JWAC-2): Championship Branch Prediction in conjunction with ISCA-38, San Jose, CA, Jun. 2011. (pdf)
  • L. Duan, Y. Zhang, B. Li and L. Peng, “Universal Rules Guided Design Parameter Selection for Soft Error Resilient Processors,” In Proceedings of The 2011 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, Apr. 2011. (pdf)
  • J. Chen, Z. Huang, F. Su, J.-K. Peir, J. Ho and L. Peng, “Weak Execution Ordering – Exploiting Iterative Methods on Many-Core GPUs,” In Proceedings of The 2010 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), White Plains, NY,  Mar. 2010. (pdf)
  • L. Duan, B. Li and L. Peng, “Reliability-Constrained Processor Performance Optimization via Design Parameter Selection,” In Poster session of The 18thIEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, Sep. 2009. (pdf)
  • S. Verma, D. Koppelman and L. Peng, “A Hybrid Adaptive Feedback Based Prefetcher,” In Proceedings of the 1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)
  • G. Liu, Z. Huang, J-K. Peir, X. Shi and L. Peng, “Enhancement for Accurate Stream Prefetching,” in Proceedings of the 1st JILP Data Prefetching Championship (DPC-1) in conjunction with HPCA-15, Raleigh, NC, Feb. 2009. (pdf)
  • L. Duan, B. Li and L. Peng, “Versatile Prediction and Fast Estimation of Architectural Vulnerability Factor from Processor Performance Metrics,” In Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, NC, Feb. 2009. (Acceptance rate: 35 / 184 = 19%) (pdf)
  • R. Tao, L. Yang, L. Peng, B. Li and A. Cemerlic, “A Case Study: Using Architectural Features to Improve Sophisticated Denial-of-Service Attack Detections,” In Proceedings of the 2009 IEEE Symposium on Computational Intelligence in Cyber Security, Nashville, TN, Mar. 2009. (pdf)
  • L. Peng, W. Lu and L. Duan, “Power Efficient IP Lookup with Supernode Caching,” In Proceedings of the 50th IEEE Global Communications Conference (Globecom),  Washington, DC, Nov. 2007. (pdf)
  • L. Peng, J-K. Peir, T. K. Prakash, Y-K. Chen, D. Koppelman, “Memory Performance and Scalability of Intel’s and AMD’s Dual-Core Processors: A Case Study,” In Proceedings of the 26th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA, Apr. 2007. (pdf)
  • L. Yang, L. Peng, “SecCMP: A Secure Chip-Multiprocessor Architecture,” In Proceedings of the First Workshop on Architectural and System Support for Improving Software Dependability (ASID) in conjunction with ACM ASPLOS XII, San Jose, CA, Oct. 2006. (pdf)
  • X. Shi, Z. Yang, J-K. Peir, L. Peng, Y-K. Chen, V. Lee, and B. Liang, “Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors”, In Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Rhodes Island, Greece. Apr. 2006. (acceptance rate: 125/531 = 24%) (pdf)
  • L. Peng, J-K. Peir and K. Lai, “Signature Buffer: Bridging Performance Gap between Registers and Caches”, In Proceedings of the 10th IEEE International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, Feb. 2004. (acceptance rate: 27/153 = 18%) (pdf)
  • L. Peng, J. Song, S. Ge, Y-K. Chen, V. Lee, J-K. Peir, and B. Liang, “Case Studies: Memory Behavior of Multithreaded Multimedia and AI Applications”, In Proceedings of Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7) in conjunction with IEEE HPCA-10, Madrid, Spain, Feb. 2004. (pdf)
  • Q. Ma, J-K. Peir, L. Peng and K. Lai, “Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores”, Best Paper Award, Processor Architecture Track, In Proceedings of IEEE International Conference on Computer Design’01 (ICCD’01), Austin, TX, Sept. 2001. (pdf)

Refereed Journal Publications:

  • S.-M. Chen, L. Peng, S. Irving, Z. Zhao, W. Zhang, and A. Srivastava, “qSwitch: Dynamical Off-Chip Bandwidth Allocation between Local and Remote Accesses”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (pdf).
  • L. Travis, L. Walker, S. Chen, and L. Peng, “Soft Error Resilience of Big Data Kernels through Algorithmic Approaches,” accepted by Springer Journal of Supercomputing. (pdf).
  • Z. Zhao, A. Srivastava, L. Peng, S.-M. Chen, and S. Mohanty, “A Novel Switchable Pin Method for Regulating Power in Chip-Multiprocessor”, accepted by Integration, The VLSI Journal (Elsevier). (pdf).
  • C. Xie, J. Tan, M. Chen, Y. Yang, L. Peng, and X. Fu, “Emerging Technology Enabled Energy-Efficient GPGPUs Register File,” accepted by Elsevier Journal of Microprocessors and Microsystems, Vol. 50, pp. 175–188, May 2017. (pdf).
  • K. Yan, L. Peng, M. Chen, and X. Fu, “Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms,” Accepted by ACM Transactions on Design Automation of Electronic Systems(pdf)
  • Y. Zhang, L. Zhao, R. Illikkal, R. Iyer, A. Herdrich, and L. Peng, “QoS Management on Heterogeneous Architecture for Multi-progammed, Parallel and Domain-Specific Applications,” Accepted by IEEE Systems Journal. (pdf)
  • S.-M. Chen, S. Irving, L. Peng, Y. Hu, Y. Zhang, A. Srivastava, “Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors,” in IEEE Transactions on Parallel and Distributed Systems, Vol. 28, Issue 1, Jan. 2017. (pdf)
  • Y. Lu, X. Wang, W. Zhang, H. Chen, L. Peng, and W. Zhao, “Performance Analysis of Multimedia Retrieval Workloads Running on Multicores,” in IEEE Transactions on Parallel and Distributed Systems, Vol. 27, No. 11, Nov. 2016. (pdf)
  • S. Chen, G. Bronevetsky, L. Peng, B. Li, and X. Fu, “Soft Error Resilience in Big Data Kernels through Modular Analysis,” in Springer Journal of Supercomputing, Vol. 72, Issue 4, Apr. 2016. (pdf)
  • Y. Lu, Y. Li, B. Song, W. Zhang, H. Chen, and L. Peng, “Parallelizing Image Feature Extraction Algorithms on Multi-core Platforms,” in Elsevier Journal of Parallel and Distributed Computing, Volume 92, May 2016. (pdf)
  • S.-M. Chen, S. Irving, and L. Peng, “Operational Cost Optimization for Cloud Computing Data Centers with Renewable Energy,” in IEEE Systems Journal, Vol. 10, Issue 4, Dec. 2016. (pdf)
  • Y. Zhang, S. Irving, L. Peng, X. Fu, D. Koppelman, W. Zhang, and J. Ardonne, “Design Space Exploration for Device and Architectural Heterogeneity in Chip-Multiprocessors,” In Journal of Microprocessors and Microsystems (Elsevier), Vol. 40, Pages 88-101, Feb. 2016. (pdf).
  • S.-M. Chen, L. Peng, Y. Hu, Z. Zhao, A. Srivastava, Y. Zhang, J. Choi, B. Li, and E. Song, “Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching,” In IEEE Transactions on Emerging Topics in Computing, Dec. 2015. (pdf).
  • S. Chen, G. Bronevetsky, B. Li, M. Casas, and L. Peng, “A Framework For Evaluating Comprehensive Fault Tolerance Mechanisms In Numerical Programs,” In Journal of Supercomputing (Springer). Aug. 2015. (pdf).
  • Y. Zhang, L. Duan, B. Li, L. Peng, S. Sadagopan, “Cross-architecture Prediction Based Scheduling for Energy Efficient Execution on Single-ISA Heterogeneous Chip-multiprocessors,” In Journal of Microprocessors and Microsystems (Elsevier), Volume 39, Issues 4–5, June–July 2015, Pages 271–285. (pdf)
  • Y. Zhang, S. Chen, L. Peng, S.-M. Chen, “NBTI Alleviation on FinFET-made GPUs by Utilizing Device Heterogeneity,” In Integration, The VLSI Journal (Elsevier),  Volume 51, Pages 10–20, Sep. 2015. (pdf)
  • L. Duan, Y. Zhang, B. Li, and L. Peng, “Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules,” In IEEE Transactions on Computers, Volume 63 , Issue 9, pages 2201 – 2214, Sep. 2014. (pdf).
  • Y. Zhang, L. Duan, B. Li, L. Peng, and X. Fu, “Design Configuration Selection for Hard-error Reliable Processors via Statistical Rules”, In Journal of Microprocessors and Microsystems, Volume 38, Issue 1, Feb. 2014, pages 22–30. (pdf).
  • L. Duan, L. Peng, and B. Li, “Predicting Architectural Vulnerability on Multi-Threaded Processors under Resource Contention and Sharing,” In IEEE Transactions on Dependable and Secure Computing, Vol. 10(2), pages 114-127, Mar.-Apr. 2013. (pdf).
  • Q. Yu, B. Li, Z. Fang, and L. Peng, “Model Guided Adaptive Design and Analysis in Computer Experiment”, In Statistical Analysis and Data Mining, Volume 5, Issue 5, pages 399–409, October 2012. (pdf).
  • G. Liu, Z. Huang, J.-K. Peir, X. Shi and L. Peng, “Enhancement for Accurate and Timely Stream Prefetching,” In Journal of Instruction-Level Parallelism, vol. 13, Jan. 2011. (pdf)
  • S. Verma, D. Koppelman, and L. Peng, “Efficient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness,” In Journal of Instruction-Level Parallelism, vol. 13, Jan. 2011. (pdf)
  • B. Li, L. Duan and L. Peng, “Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions,” In IEEE Transactions on Computers, Special Section on System Level Design of Reliable Architectures, Vol 59(5), pp. 593-607, May 2010. (pdf)
  • R. Tao, L. Yang, L. Peng and B. Li, “A Host-Based Intrusion Detection System Using Architectural Features to Improve Sophisticated Denial-of-Service Attack Detections,” In International Journal of Information Security and Privacy, Vol. 4(1), 18-31, Jan.-Mar. 2010. (pdf)
  • Q. Yu, B. Li, Z. Fang and L. Peng, “An adaptive sampling scheme guided by BART – with an application to predict processor performance,” In Canadian Journal of Statistics, Vol 38(1), pp. 136-152, Mar. 2010. (pdf)
  • Y. Zhang, L. Peng, W. Lu, L. Duan and S. Rai, “Expediating IP Lookups with Reduced Power via TBM and SST Supernode Caching,” In Computer Communications, vol 33(3), pp. 390-397, Feb. 2010. (pdf)
  • B. Li, L. Peng and B. Ramadass. “Accurate and Efficient Processor Performance Prediction via Regression Tree Based Modeling,” In Journal of Systems Architecture. Vol. 55 (10-12), pp. 457-467, Oct.-Dec., 2009 (pdf)
  • L. Yang, L. Peng and B. Ramadass, “SecCMP: Enhancing Critical Secret Protection in Chip-Multiprocessors,” In International Journal of Information Security and Privacy, vol.2(4), pp. 54-66, Oct.-Dec. 2008. (pdf)
  • L. Peng, J-K. Peir, T. K. Prakash, C. Staelin, Y-K. Chen, D. Koppelman, “Memory Hierarchy Performance Measurement of Commercial Dual-Core Desktop Processors,” In Journal of Systems Architecture, vol 54(8), pp. 816-828, Aug. 2008. (pdf)
  • B. Li, L. Peng and B. Ramadass, “Efficient MART-Aided Modeling for Microarchi-tecture Design Space Exploration and Performance Prediction,” In ACM SIGMETRICS Performance Evaluation Review, Special issue on ACM SIGMETRICS ’08, Volume 36 Issue 1, June 2008, pp. 439-440.  (pdf)
  • T. K. Prakash and L. Peng, “Performance Characterization of SPEC CPU2006 Benchmarks on Intel Core 2 Duo Processor,” In ISAST Transactions on Computers and Software Engineering, No. 1, Vol 2, pp. 36-41, 2008. (pdf)
  • L. Peng, J-K. Peir and K. Lai, “A New Memory Hierarchy Layer for Zero-cycle Load”. In Journal of Instruction-Level Parallelism, vol.6, Sept. 2004. (acceptance rate: 15%) (pdf)
  • L. Peng, J-K. Peir, Q. Ma and K. Lai, “Address-Free Memory Access Based on Program Syntax Correlation of Loads and Stores”, In IEEE Transactions on VLSI systems, June, 2003. (Invited Paper) (pdf)

Book Chapters:

  • Y. Zhang, S. Chen, L. Peng, and S.-M. Chen, “FinFET and Reliability Considerations of Next-generation Processors,” In “Nano-CMOS and Post-CMOS Electronics: Devices and Modelling,” Institution of Engineering and Technology (IET), 2015.
  • L. Peng, L. Yang and B. Ramadass, “Architectural Support for Enhancing Critical Secrets Protection in Chip-Multiprocessors,” In “Pervasive Information Security and Privacy Developments: Trends and Advancements,” IGI Global Press, Jun. 2010.

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