Lu Peng

     Assistant Professor


Address:
     Louisiana State University
     Dept. of Elect. & Computer Eng.
     Baton Rouge, LA 70803-5901


Tel:      225-578-5535
Fax:     225-578-5200
E-mail: lpeng@lsu.edu

 

Research Interests

Computer Architecture, Microarchitecture, System Performance Analysis, Network Processor

 

Teaching

·        Spring 2008, EE7720 Advanced Computer Architecture

·        Fall 2007, EE4700-1 Parallel Programming

·        Spring 2007, EE7700-2 Topics in Processor Design

·        Fall 2006, EE7720 Advanced Computer Architecture 

·        Spring 2006, EE7000-7  Topics in Processor Design

·        Fall 2005, EE7700-2 Computer Architecture Principles

 

Education

·        Ph.D., Computer Engineering, University of Florida.

·        M.E., Computer Science & Engineering, Shanghai Jiaotong University, China.

·        B.E., Computer Science & Engineering, Shanghai Jiaotong University, China.

 

Experience

  • Assistant Professor, ECE dept., LSU                                                                                                    Jul. 2005 - Now

·        Research Intern, Intel Microarchitecture Research Lab / China Research Center                                               Jun. 2003 - Nov. 2003

  • Research Assistant, University of Florida                                                                                                           Jan. 2001 - Apr. 2005

 

Grants

·        Louisiana State University, Faculty Research Grant, 2006-2007

·        Louisiana Board of Regents, Research Competitiveness Subprogram, 2006-2009

·        Louisiana BoR, NSF-EPSCoR, PFund, 2006-2007

·        Louisiana State University, Summer Stipend Grant, 2007

·        ORAU Ralph E. Powe Junior Faculty Enhancement Awards, 2007

·        Louisiana Board of Regents, Traditional Enhancement Program, 2007-2008 (Co-PI).

 

Publications

  • L. Peng, J-K. Peir, T. K. Prakash, C. Staelin, Y-K. Chen, D. Koppelman, “Memory Hierarchy Performance Measurement of Commercial Dual-Core Desktop Processors”, Accepted by Journal of Systems Architecture. (pdf)
  • B. Li, L. Peng and B. Ramadass, “Efficient MART-Aided Modeling for Microarchitecture Design Space Exploration and Performance Prediction,” (extended abstract), Accepted by 2008 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2008), Annapolis, MD, Jun. 2008. (pdf)
  • T. K. Prakash and L. Peng, “Performance Characterization of SPEC CPU2006 Benchmarks on Intel Core 2 Duo Processor,” Accepted by ISAST Transactions on Computers and Software Engineering. (pdf)
  • L. Peng, W. Lu and L. Duan, “Power Efficient IP Lookup with Supernode Caching,” In Proceedings of the 50th IEEE Global Communications Conference (Globecom),  Washington, DC, Nov. 2007. (pdf)
  • L. Peng, J-K. Peir, T. K. Prakash, Y-K. Chen, D. Koppelman, “Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study,” In Proceedings of the 26th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA, Apr. 2007. (pdf)
  • L. Yang, L. Peng, “SecCMP: A Secure Chip-Multiprocessor Architecture,” In Proceedings of the First Workshop on Architectural and System Support for Improving Software Dependability (ASID) in conjunction with ACM ASPLOS XII, San Jose, CA, Oct. 2006. (pdf)
  • X. Shi, Z. Yang, J-K. Peir, L. Peng, Y-K. Chen, V. Lee, and B. Liang, "Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors", In Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Rhodes Island, Greece. Apr. 2006. (acceptance rate: 24%) (pdf)

·        L. Peng, J-K. Peir and K. Lai, "A New Memory Hierarchy Layer for Zero-cycle Load". In Journal of Instruction-Level Parallelism, vol.6, Sept. 2004. (acceptance rate: 15%) (pdf)

·        L. Peng, J-K. Peir and K. Lai, "Signature Buffer: Bridging Performance Gap between Registers and Caches", In Proceedings of IEEE International Symposium on the 10th High Performance Computer Architecture (HPCA-10), Madrid, Spain, Feb. 2004. (acceptance rate: 17%) (pdf)

·        L. Peng, J. Song, S. Ge, Y-K. Chen, V. Lee, J-K. Peir, and B. Liang, "Case Studies: Memory Behavior of Multithreaded Multimedia and AI Applications", In Proceedings of Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7) in conjunction with IEEE HPCA-10, Madrid, Spain, Feb. 2004. (pdf)

·        L. Peng, J-K. Peir, Q. Ma and K. Lai, "Address-Free Memory Access Based on Program Syntax Correlation of Loads and Stores", In IEEE Transactions on VLSI systems, June, 2003. (Invited Paper) (pdf)

·        Q. Ma, J-K. Peir, L. Peng and K. Lai, "Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores", Best Paper Award, In Proceedings of IEEE International Conference on Computer Design'01 (ICCD'01), Austin, TX, Sept. 2001. (pdf)

 

Processional Services

·        Program Committee Member, The 20th IASTED International Conference on Parallel and Distributed Computing and Systems.

·        Program Committee Member, International Conference on Parallel Processing 2008.

·        Program Committee Member, International Conference on Parallel Processing 2007.

·        Session Chair, International Performance Computing and Communications Conference, 2007.

 

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