Chemora: a PDE Solving Framework for Modern HPC Architectures Erik Schnetter, Marek Blazewicz, Steven R. Brandt, David M. Koppelman, and Frank Löffler, Computing in Science and Engineering, to appear. Show Abstracts
Discovering Barriers to Efficient Execution, Both Obvious and Subtle, Using Instruction-Level Visualization David M. Koppelman and Chris J. Michael, First Workshop on Visual Performance Analysis, New Orleans, Louisiana, USA, November 2014. Show Abstracts
From Physics Model to Results: An Optimizing Framework for Cross-Architecture Code Generation Marek Blazewicz, Ian Hinder, David M. Koppelman, Steven R. Brandt, Milosz Ciznick, Michal Kierzynka, Frank Löffler, Erik Schnetter, and Jian Tao, Scientific Programming, vol.~21, pp 1-16, 2013. Show Abstracts
The Interaction and Relative Effectiveness of Hardware and Software Data Prefetch S. Verma and David M. Koppelman, Journal of Circuits, Systems, and Computers (special issue on Interaction between Compilers and Computer Architectures) vol. 21, no. 2, pp 1.21, 2012. Show Abstracts
A Massive Data Parallel Computational Framework for Petascale/Exascale Hybrid Computer Systems Marek Blazewicz, Steven R. Brandt, Peter Diener, David M. Koppelman, Krzysztof Kurowski, Frank Loeffler, Erik Schnetter, and Jian Tao, International Conference on Parallel Computing, September 2011.
A Penalty-Sensitive Branch Predictor Yue Hu, David M. Koppelman, Lu Peng, The Journal of Instruction-Level Parallelism 2nd JILP Workshop on Computer Architecture Competitions (JWAC-2): Championship Branch Prediction, held in conjunction with The 38th International Symposium on Computer Architecture, June 2011. Presentation (680 kB Powerpoint) Show Abstracts
Efficient Prefetching with Hybrid Schemes and Use of Program Feedback to Adjust Prefetcher Aggressiveness Santhosh Verma, David M. Koppelman, and Lu Peng, The Journal of Instruction-Level Parallelism, 13 (2011) 1-14 (January 2011). Show Abstracts
The Effects On Branch Prediction When Utilizing Control Independence Chris J. Michael and David M. Koppelman, The IEEE International Parallel & Distributed Processing Symposium PhD Forum, April 2010. Show Abstracts
Spotlight--a Low Complexity Highly Accurate Profile-Based Branch Predictor Santhosh Verma, Benjamin Maderazo and David M. Koppelman, in the proceeding of the 28th IEEE International Performance Computing and Communications Conference, Phoenix, AZ, December 2009. Show Abstracts
Memory Hierarchy Performance Measurement of Commercial Dual-Core Desktop Processors L. Peng, J-K Peir, T. K. Prakash, C. Staelin, Y-K. Chen, and D. Koppelman, Journal of Systems Architecture, vol 54, no. 8, pp. 816-828, Aug. 2008. Show Abstracts
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: a Case Study Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-Kuang Chen, and David Koppelman, the 26th IEEE International Performance Computing and Communications Conference (IPCCC), New Orleans, LA, Apr. 2007.
The Impact of Fetch Rate and Reorder Buffer Size On Speculative Pre-Execution David M. Koppelman, Workshop on Duplicating, Deconstructing, and Debunking Held in conjunction with the 30th International Symposium on Computer Architecture June 8, 2003, pp. 64-75. Presentation (813 kB PDF) Show Abstracts
The Benefit of Multiple Branch Prediction On Dynamically Scheduled Systems David M. Koppelman, Workshop on Duplicating, Deconstructing, and Debunking Held in conjunction with the 29th International Symposium on Computer Architecture May 26, 2002, pp. 42-51. Presentation (455 kB PDF) Show Abstracts
Neighborhood Prefetching On Multiprocessors Using Instruction History David M. Koppelman, International Conference on Parallel Architectures and Compilation Techniques, October 2000, pp. 123-132. Longer Version (211 kB PDF) Presentation (272 kB PDF) Show Abstracts
Using Predictions of Non-Regular Memory Access Patterns to Improve Multiprocessor Cache Performance (Neighborhood Prefetching) David M. Koppelman, LSU ECE Department Seminar, March 1999. Show Abstracts
Speculative Multiprocessor Cache Line Actions Using Instruction and Line History David M. Koppelman, The 10th International Conference on Parallel & Distributed Computing Systems, New Orleans, Louisiana, October 1997, pp. 401-406. Presentation (225 kB PDF) Show Abstracts
A Multiprocessor Memory Processor for Efficient Sharing and Access Coordination David M. Koppelman, Workshop on Mixing Logic and DRAM, International Symposium on Computer Architecture, June 1997. Presentation (319 kB PDF) Show Abstracts
Sticky States in Banyan Network Queues and Their Application to Analysis David M. Koppelman, The Journal of Parallel and Distributed Computing, vol. 40, pp. 147-161, 1997. Show Abstracts
A Lower Bound On the Average Physical Length of Edges in the Physical Realization of Graphs David M. Koppelman, Parallel Processing Letters, vol. 6, no. 1, pp. 137-143, 1996. Show Abstracts
Congested Banyan Network Analysis Using Congested-Queue States and Neighboring-Queue Effects David M. Koppelman, IEEE/ACM Transactions on Networking, vol. 4, no. 1, pp. 106-111, February 1996. Show Abstracts
Related technical report: Congested banyan network analysis using congested-queue states and neighboring-queue effects, David M. Koppelman, Technical Report, Louisiana State University, Baton Rouge, LA, September 1995. Manuscript (275 kB PDF)
An Analysis of Banyan Networks Offered Traffic with Geometrically Distributed Message Lengths I-Pyen Lyaw and David M. Koppelman, IEE Proceedings - Communications, vol. 142, no. 5, pp. 285-291, October 1995. Show Abstracts
Reducing PE/Memory Traffic in Shared Memory Multiprocessors by the Difference Coding of Memory Addresses David M. Koppelman, IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 11, pp. 1156-1168, November 1994. Show Abstracts
Also appearing as: Reducing PE/memory traffic in shared memory multiprocessors by the difference coding of memory addresses, David M. Koppelman, in International Conference on Parallel Processing, August 1992, vol. I, pp. 53-56.
Also appearing as: A self-routing permutation network, David M. Koppelman and A. Yavuz Oruç, in International Conference on Parallel Processing, August 1989, vol. I, pp. 288-295.
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