| Instruction Set | SPARC V8a (Subset of V9 used on 32-bit OS.) |
| Instruction Issue | Dynamically scheduled. |
| Branch Predictor | YAGS, with 16-bit global history. |
| Jump Predictor | gshare-like jump target buffer. |
| Misprediction Recovery | Starts at instruction completion. |
| Level 1 Cache | 64 kiB, 1 cycle load latency, 64-byte line. |
| Level 2 Cache | 256 kiB, 18 cycle load latency, 64-byte line. |
| Miss Latency | At least 100 cycles. |
| Issue Width | Four-Way (Includes fetch, decode, issue, and commit.) |
| Reorder Buffer | 128 entries. |
| Branch Predictor | YAGS, with 16-bit global history. |
| Fetch | Single-ported icache; simple next line predictor. |
| Functional Units | Four integer, 2 each of other types. |