COLP'01 Program

Final Program: Workshop on

Compilers and Operating Systems for Low Power 2001 (COLP'01)

Workshop Organizers:

Luca Benini       Mahmut Kandemir       J. Ramanujam (Ram)

Sunday, September 9, 2001Held in Conjunction with PACT'01
Hilton Barcelona HotelBarcelona, Spain


Registration Information Registration Information
Registration Form Registration Form


Hotel Information Hotel Information
Traveling to Barcelona Traveling to Barcelona

Power consumption has increasingly become important in computer systems. Current designs of processor cores are predicting power figures above 100 Watts. The management of power consumption while simultaneously delivering acceptable levels of performance is becoming a critical task with the proliferation of systems in several application domains such as wireless communication and embedded signal processing. In addition, it is important to manage power consumption in high-performance general purpose microarchitectures. It has been forecast that without significant advances in design for low power, processors of the future will consume hundreds of watts of power. We believe that an integrated hardware and software approach is required. A lot of attention has been paid to optimizing power at the circuit and gate levels. Recently, power optimizations at the architecture and software (i.e., compiler, operating system, and application) level have begun to receive attention. The purpose of this workshop is to draw together researchers and practitioners concerned with compiler and operating system support for low power for a stimulating exchange of views.

COLP 01 Final Program

8:55 - 9:00 Opening Remarks
 
9:00 - 11:00 Session 1: (30 minutes for each presentation)
 
9:00 Low Power Operating System for Heterogeneous Wireless Communication Systems
Suet-Fei Li, Roy Sutton, and Jan Rabaey
University of California - Berkeley, USA
 
9:30 Power Low Approach in a Modified Dual Priority Scheduling for Hard Real-Time Systems
M. A. Moncusi, Alex Arenas, and Jesus Labarta
Universitat Rovira i Virgili and Universitat Politecnica de Catalunya, Spain
 
10:00 A Restricted Model for the Optimal Placement of Power Management Points in Real Time Applications
Nevine AbouGazelah, Daniel Mosse, Rami Melhem, and Bruce Childers
University of Pittsburgh, USA
 
10:30 Load Balancing and Unbalancing for Power and Performance in Cluster-Based Systems
Eduardo Pinheiro, Ricardo Bianchini, Enrique Carrera, and Taliver Heath
Rutgers University, USA
 
11:00 - 11:30     Coffee Break
 
11:30 - 1:00 Session 2: (30 minutes for each presentation)
 
11:30 Energy Characterization of Embedded Real-Time Operating Systems
Andrea Acquaviva, Luca Benini, and Bruno Ricco
Universita di Bologna, Italy and Stanford University, USA
 
12:00 Propagating Constants Past Software to Hardware Peripherals
Frank Vahid and Rilesh Patel
University of California - Riverside, USA
 
12:30 Constructive Timing Violation for Improving Energy Efficiency
Toshinori Sato and Itsujiro Arita
Kyushu Institute of Technology, Japan
 
1:00 - 2:30 LUNCH
 
2:30 - 4:00 Session 3: (30 minutes for each presentation)
 
2:30 Power Modeling and Reduction of VLIW Processors
Weiping Liao and Lei He
University of Wisconsin - Madison, USA
 
3:00 Energy Mangement of Virtual Memory on Diskless Devices
Jerry Hom and Ulrich Kremer
Rutgers University, USA
 
3:30 Low Power Design of Turbo Decoder Module with Exploration of Power-Performance Trade-offs
K. C. Shashidhar, Arnout Vandecappelle, and Francky Catthoor
IMEC and Katholieke Universitaet, Belgium
 
4:00 - 4:30     Coffee Break
 
4:30 - 6:10 Session 4: (20 minutes for each presentation)
 
4:30 Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches
Paolo D'Alberto, Alexandru Nicolau, Alexander Veidenbaum and Rajesh Gupta
University of California - Irvine, USA
 
4:50 Power and Energy Impact of Loop Transformations
Hongbo Yang, Guang R. Gao, Andres Marquez, George Cai, and Ziang Hu
University of Delaware, USA
 
5:10 Buffered Tiling for Sequences of Loop Nests
Youcef Bouchebaba and Fabien Coelho
Ecole des Mines de Paris, France
 
5:30 Low Energy Clustered Instruction Fetch and Split Loop Cache Architecture for Long Instruction Word Processors
Murali Jayapala, Francky Catthoor, and Rudy Lauwereins
IMEC and Katholieke Universitaet, Belgium
 
5:50 A Fresh Look At Low-Power Mobile Computing
Michael Franz
University of California - Irvine, USA
 
6:10 - 6:20 Closing Remarks

For more information, please contact the workshop co-chairs, Luca Benini ( lbenini@deis.unibo.it) or Mahmut Kandemir ( kandemir@cse.psu.edu) or J. Ramanujam ( jxr@ece.lsu.edu)

PROGRAM COMMITTEE 
Eduard Ayguade, Univ. Politecnica de Catalunya          eduard@ac.upc.es
R. Chandramouli, Stevens Institute of Technology        rchandr1@stevens-tech.edu
Bruce Childers, University of Pittsburgh                childers@cs.pitt.edu
Marco Cornero, STMicroelectronics                       marco.cornero@st.com 
Rudi Eigenmann, Purdue University                       eigenman@ecn.purdue.edu
Manish Gupta, IBM T. J. Watson                          mgupta@us.ibm.com
Rajiv Gupta, University of Arizona                      gupta@cs.arizona.edu
Mary Janie Irwin, Penn State University                 mji@cse.psu.edu
Uli Kremer, Rutgers University                          uli@cs.rutgers.edu
Rainer Leupers, University of Dortmund                  leupers@LS12.cs.uni-dortmund.de
Diana Marculescu, Carnegie Mellon University            dianam@ece.cmu.edu
Enric Musoll, Clearwater Networks, Inc.                 enric@clearwaternetworks.com
Anand Sivasubramaniam, Penn State University            anand@cse.psu.edu
Mary Lou Soffa, University of Pittsburgh                soffa@cs.pitt.edu 
Vamsi K. Srikantam, Agilent Laboratories                vamsi@labs.agilent.com
Chau-Wen Tseng,  University of Maryland                 tseng@cs.umd.edu   
Arnout Vandecappelle, IMEC/DESICS                       vdcappel@imec.be 
N. Vijaykrishnan, Penn State University                 vijay@cse.psu.edu