Cadence Tools

From LSU ECE Wiki

Jump to: navigation, search

License Details

Product Name Product Code Number of Licenses
AMS Designer with Flexible Analog Simulation 70020 300
Encounter RTL Compiler - GXL option RC300 300
Encounter RTL Compiler - XL RC200 300
VoltageStorm (Gate and Transistor)" VS2 300
Cadence SiP RF Layout GXL SIP525 300
Generator to generate Assura compatible verification decks PASASG 300
Virtuoso(R) Analog Design Environment - GXL 95220 300
Encounter Timing System-XL FE725 300
Encounter Library Characterizer - XL ELC200 300
Cadence SiP Digital Layout GXL SIP325 300
Allegro(R) PCB Design CIS - XL" PX3710 300
Generator to generate Dracula compatible verification decks PASDRG 300
Encounter Timing System - L FE625 300
Encounter (TM) Conformal - GXL (a.k.a Conformal Custom) CFM300 300
Assura(TM) Multiprocessor Option" 72150 300
Cadence SiP Digital Architect SIP125 300
(R) Simulation Analysis Environment (SimVision) 25010 300
Pcell Generator PASPCG 300
Cadence(R) Design Framework Integrator's Toolkit 12141 300
AMS Option to Incisive(TM) 29370 300
Virtuoso(R) Analog Design Environment XL 95210 300
Virtuoso(R) Schematic Editor XL 95115 300
Diva(R) Physical Verification and Extraction Suite 72150 300
Virtuoso(R) Schematic Editor HSPICE Interface 276 300
Cadence SiP RF Architect - XL SIP410 300
Allegro(R) PCB Design HDL - XL PX3700 300
USB UVC UVC101 300
Cadence(R) NC-VHDL Simulator 28400 300
Virtuoso(R) Layout Suite - GXL 95321 300
Cadence SiP Digital SI XL) SIP215 300
Cadence(R) SKILL Development Environment 900 300
Assura(TM) Graphical User Interface Option 72140 300
Virtuoso(R) Analog HSPICE Interface Option 32760 300
Allegro(R) PCB Librarian - XL PX3500 300
Allegro(R) AMS Simulator PS2200 300
Virtuoso(R) Spectre(R)-RF Option for 38500 38520 300
Dracula(R) Graphical User Interface 365 300
Allegro(R) Package Designer - XL PA6620 300
Cadence(R) NC-Sim Mixed-Language Simulator 28000 300
Incisive Enterprise Manager EMG100 300
PCI Express 1.1 Root Complex UVC UVC103 300
PCI Express 1.1 End Point UVC UVC102 300
eVerification Component (eVC) for Ethernet protocol EVC1006 300
Allegro(R) PCB SI - XL PX3100 300
Cadence(R) OASIS for RFDE 32101 300
Virtuoso(R) Analog Oasis Run-Time Option 32100 300
Virtuoso(R) Chip Assembly Router 3300 300
AMBA AXI UVC UVC107 300
Virtuoso(R) Multi-mode Simulation 90001 300
Error Cell Generator PASECG 300
Virtuoso(R) EDIF 200 Writer 945 300
Virtuoso(R) Schematic Editor Verilog(R) Interface 21400 300
Virtuoso(R) EDIF 200 Reader 940 300
e Verification Component (eVC) for PCI 2.2/2.3 protocol EVC1004 300
Virtuoso(R) UltraSim Full-chip Simulator 33500 300
Generator to generate Diva compatible verification decks PASDIG 300
ESL Option For Incisive Enterprise Simulator – XL 29656 300
Incisive Enterprise Simulator - XL 29651 300
Assura(TM) Layout Vs. Schematic Verifier 72120 300
Virtuoso(R) Schematic VHDL Interface 21060 300
Virtuoso(R) Spectre(R) Simulator 38500 300
Virtuoso(R) AMS Designer Environment 70000 300
Graphical Technology Editor PASTGE 300
AMBA AHB UVC UVC100 300
Virtuoso QRC Extraction - XL QRCX300 300
Encounter Diagnostics Engine - XL ET009 300
SOC Encounter - XL (aka Cadence (R) SOC Encounter - GPS) FE200GPS 300
Assura(TM) Design Rule Checker 72110 300
Encounter(R) True-time Test - GXL ET002 300
Incisive Formal Verifier 23560 300
Encounter(R) Test Architect - XL ET001 300
Virtuoso QRC Extraction - L QRCX100 300
PacifIC Static Noise Analyzer for Custom Digital ICs CM00100 300
Personal tools