## LSU EE 4720 -- Spring 2008 -- Computer Architecture
#
## MIPS Overview
# Time-stamp: <4 March 2008, 15:53:06 CST, koppel@buz>
## Note
#
# This set based on EE 3755 Spring 2002 sets 9, 10, and 12.
## Contents
#
# Machine Language Basics
# Machine Languages Covered in ECE Courses
# Instructions, Registers, Immediates, and Memory
# Basic Three-Register Instructions
# Other Basic Instructions
# Instruction Coding
# Miscellaneous Integer Arithmetic Instructions
# Pseudo Instructions
#
# Types of Control-Transfer Instructions
# A Simple Jump Instruction
# A Branch Instruction
# More Branch Instructions
# More Jump Instructions
# Procedure Call Example
# Typical CTI Uses
#
# Load Byte (Unsigned)
# Store Byte
# Load Byte
# Load Word, Store Word
# Load and Store Half
# Array Access Examples
# Histogram Program
## References
#
# :PH: Patterson & Hennessy, "Computer Organization & Design"
# :Mv1: MIPS Technologies, "MIPS32 Architecture for Programmers Vol I: Intro"
# :Mv2: MIPS Technologies, "MIPS32 Architecture for Programmers Vol II: Instr"
## Objectives
#
# Understand MIPS Register and Memory Organization
# Understand MIPS Instructions
# Read programs using instructions, write program using instructions.
# Understand MIPS Instruction Coding and Formats
# Determine binary coding from assembly, and vice versa.
# Ability to Learn New Instructions from MIPS Documentation
# Write Simple Assembly Language Programs
################################################################################
## Machine Language Review
# :PH: 3
# :Def: Machine Language
#
# The language understood by the computer processor itself.
# An ISA describes the machine language, plus other details.
#
# :Def: Machine Code
#
# All or part of a machine language program.
# :Def: High-Level Language
#
# A computer programming language for humans.
#
# Examples: C, Basic, Java, Fortran.
#
# A program in a high-level language may be converted into machine
# language and then run.
#
# A high-level language can be converted into the machine language of
# (compiled for) many machines.
# :Def: Assembly Language
#
# A language for humans used to prepare machine code.
#
# Assembly language is human readable, machine language is not.
# (At least without great effort or rare talent.)
v#
# For each machine language there is usually one assembly language.
# (In principle there could be many assembly languages for each
# machine language.)
#
# The machine language and corresponding assembly language are sometimes
# known by the same name, for example MIPS.
#
# Almost all examples will be in assembly language.
## A Short MIPS Assembly Language Program
#
#
add $s1, $s2, $s3 # s1 = s2 + s3
sub $s1, $s4, $s1 # s1 = s4 - s1
#
# Comments start with a #.
#
# $s1-$s4 are storage locations called /registers/.
#
# Each register holds 32 bits.
# The program again, showing initial, intermediate, and final register values.
#
# Initial: s1 = 10, s2 = 20, s3 = 30, s4 = 40
add $s1, $s2, $s3
# s1 = 50, s2 = 20, s3 = 30, s4 = 40
sub $s1, $s4, $s1
# Final: s1 =-10, s2 = 20, s3 = 30, s4 = 40
# The program again, in three forms:
#
# High-Level (C) Assembly (MIPS) Machine (MIPS)
# a = b + c; add $s1, $s2, $s3 0x02538820
# a = d - a; sub $s1, $s4, $s1 0x02918822
#
# Note: the relationship between high-level code and assembly code
# is rarely one machine instruction per high-level statement.
################################################################################
## Instructions, Registers, Immediates, and Memory
# :PH: 3.3
# :Mv1: 2.8.4, 2.8.5 MIPS register descriptions
## Where MIPS Instructions Get Data
#
# Immediates: Data stored in instruction.
# Registers: A small number (66) of high-speed 32-bit storage locations.
# Memory: A large number (2^32) of low-speed 8-bit storage locations.
addi $a0, $a0, 1 # Gets data from register ($a0) and immed. (1)
lbu $t1, 0($a0) # Gets data from memory (address in $a0)
## What MIPS Instructions can Modify
#
# Registers
# Memory
addi $a0, $a0, 1 # Modifies register, $a0.
sb $t1,-1($a0) # Modifies memory, address is $a0-1
## Registers
#
# Used in this Set (MIPS has additional registers.)
#
# $0-$31: 32 bits, General Purpose Registers (GPRs). See GPR names below.
# PC: 32 bits (30 bits), Program Counter
# $lo, $hi: 32 bits, Registers used for multiplication and division.
# $f0-$f31: 32 bits, Floating Point (coprocessor 1) Registers
## General-Purpose Register (GPR) Names
#
# There are 32 (arguably 31) general purpose registers (GPRs).
#
# Each register holds 32 bits. (MIPS-32)
#
# Each has a name and a number.
#
# Numbers range from 0 to 31.
#
# Names indicate suggested use.
#
# Either names or numbers can be used in assembly language.
# In machine language only numbers are used.
#
# Ways to Reference GPR Number 1 (varies by assembler, textbook author, etc.)
#
# By number: 1, $1, r1, R1
#
# By name: $at
# List of General-Purpose Registers. (Will be explained later.)
# See :PH: A-23
#
# The value of register 0 ($zero) is always zero.
#
# The value of the other registers is the last value written.
#
#
## Names Numbers Suggested Usage
# $zero: 0 The constant zero.
# $at: 1 Reserved for assembler.
# $v0-$v1: 2-3 Return value
# $a0-$a3: 4-7 Argument
# $t0-$t7: 8-15 Temporary (Not preserved by callee.)
# $s0-$s7: 16-23 Saved by callee.
# $t8-$t9: 24-25 Temporary (Not preserved by callee.)
# $k0-$k1: 26-27 Reserved for kernel (operating system).
# $gp 28 Global Pointer
# $sp 29 Stack Pointer
# $fp 30 Frame Pointer
# $ra: 31 Return address.
# :Example:
#
# The two instructions below are identical, the first uses register
# names, the second uses register numbers.
add $s1, $t2, $sp
add $17, $10, $29
####
## Memory
#
# Memory consists of 2^32 locations. [MIPS-64 has 2^64 locations.]
#
# Each location stores 8 bits, called a character or a byte.
#
# Each location has an address, an integer ranging from 0 to 4294967295
#
# Memory access is usually slower than register access.
# :Example:
#
# Examples of instructions accessing memory. The first loads
# something from memory into a register, the second stores something
# from a register to memory. These will be covered in detail later.
lw $4, 0($19)
sw $31, 72($sp)
####
## Immediates
#
# An immediate is a constant value stored in the instruction itself.
#
# In MIPS immediate are usually 16 bits and can be interpreted as
# signed or unsigned numbers (depending on the instruction).
# :Example:
#
# An instruction using an immediate, in this case 100.
addi $1, $2, 100
################################################################################
## Basic Three-Register Instructions
# :PH: Throughout Chapter 3.
# :Mv2: A complete list of instructions.
# The three-register instructions each read two source registers and
# write one destination register.
## The Plain Old Add Instruction
#
# :Syntax: ADD rd, rs, rt
# rd <- rs + rt
#
# How to read the syntax shown above:
#
# The mnemonic (name) of the instruction is ADD. A lower-case
# version of the mnemonic (add) should be used in assembly language.
#
# The instruction has three operands, rd, rs, rt.
# These symbols refer to general-purpose register operands.
# In assembly language they would be replaced by a register name or number.
# (Machine language coding will be covered later.)
#
# The line rd <- rs + rt indicates what the instructions does.
#
# ADD instruction assembly language examples:
add $1, $2, $3
add $s1, $t2, $v1
# The instruction below is NOT an add instruction because $rt is not a GPR.
# A "strict" assembler would NOT be able to convert that in to machine
# code. (A "liberal" assembler would correct the mistake by replacing
# "add" with "addi".)
add $1, $2, 100
# There is an instruction that can take the constant 100, "addi."
## Other Basic Three-Operand Instructions
#
# :Syntax: SUB rd, rs, rt
# rd <- rs - rt
#
# :Syntax: AND rd, rs, rt
# rd <- rs & rt
#
# :Syntax: OR rd, rs, rt
# rd <- rs | rt
#
# :Syntax: NOR rd, rs, rt
# rd <- ~( rs | rt )
#
# :Syntax: XOR rd, rs, rt
# rd <- rs ^ rt
#
# :Syntax: SLT rd, rs, rt # Set less than.
# rd <- rs < rt ? 1 : 0;
# Comparison as signed integers.
# There's no SGT, which makes sense if you think about it.
#
# :Syntax: SLLV rd, rs, rt # Shift Left Logical Variable
# rd <- rs << rt[4:0]
# Note: Only five low-order bits of rt are used (other bits ignored).
#
# :Syntax: SRLV rd, rs, rt # Shift Right Logical Variable
# rd <- rs >> rt[4:0]
# Note: "Vacated" bit positions are zero.
# Note: Only five low-order bits of rt are used (other bits ignored).
#
# :Syntax: SRAV rd, rs, rt # Shift Right Arithmetic Variable
# rd <- {rs[31],rs[31],..., rs >> rt[4:0] }
# Note: Sign is extended: bit (rs[31]) placed in vacated positions.
# Note: Only five low-order bits of rt are used, the rest are ignored.
# :Example:
#
# Simplified assembler for the following line of C:
#
# x = a + b - ( c + d );
#
# Asm regs: x, $8; a, $9; b, $10; c, $11; d, $12
add $8, $9, $10 # a + b
add $13, $11, $12 # c + d
sub $8, $8, $13
####
# :Example:
#
# Use of register zero.
#
# Simplified assembler for the following line of C:
#
# x = -a;
# y = -1;
#
# Asm regs: x, $8; a, $9; y, $10
# Reminder: register $0 is always zero.
sub $8, $0, $9
nor $10, $0, $0
####
# :Example:
#
# Simplified assembler for the following line of C:
#
# x = ( ir >> off ) & mask;
#
# Asm regs: x, $8; ir, $9; off, $10; mask, $11.
srlv $8, $9, $10
and $8, $8, $11
####
# :Example:
#
# Simplified assembler for the following line of C:
#
# x = a + b > ( c & mask | d );
#
# Asm regs: x, $8; a, $9; b, $10; mask, $11; c, $12; d, $13
add $20, $9, $10 # a + b
and $21, $12, $11 # c & mask
or $21, $21, $13 # c & mask | d
slt $8, $21, $20 # >
################################################################################
## Other Basic Instructions
# :PH: Throughout Chapter 3.
# :Mv2: A complete list of instructions.
# :Def: Immediate
#
# A constant stored in the instruction itself.
#
# In MIPS most immediates are 16 bits, including the ones in this section.
## Assembler Metasyntactic Symbols for Immediates
#
# Metasyntactic symbols are used in syntax descriptions.
#
# immed: 16-bit immediate, for general use.
# sa: 5-bit immediate (shift amount), used in shift instructions.
## The Plain-Old Addi Instruction
#
# :Syntax: ADDI rt, rs, immed # Add Immediate
# rt <- rs + sign_extend(immed)
#
# Notes on the syntax above.
#
# The destination register is now called rt.
#
# Symbol immed refers to a 16 bit value which is stored in the instruction.
#
# For the ADDI instruction immed is interpreted as a signed integer.
## Some More Instructions
#
# The following are NOT MIPS32 instructions:
# SUBI, NORI
#
# :Syntax: ANDI rt, rs, immed # And Immediate
# rt <- rs & immed
#
# :Syntax: ORI rt, rs, immed
# rt <- rs | immed
#
# :Syntax: XORI rt, rs, immed
# rt <- rs ^ immed
#
# :Syntax: SLTI rt, rs, immed # Set Less Than Immediate
# rt <- rs < sign_extend(immed) ? 1 : 0;
# Comparison as signed integers, immed is sign-extended.
# There's no SGT, which makes sense if you think about it.
#
# :Syntax: SLL rd, rt, sa # Shift Left Logical
# rd <- rt << sa
#
# :Syntax: SRL rd, rt, sa # Shift Right Logical
# rd <- rt >> sa
# Note: "Vacated" bit positions are zero.
#
# :Syntax: SRA rd, rt, sa # Shift Right Arithmetic
# rd <- {rt[31],rt[31],..., rs >> sa }
# Note: Sign is extended: bit (rt[31]) placed in vacated positions.
#
# :Syntax: LUI rt, immed # Load Upper Immediate
# rt <- {immed,16'b0}
# :Example:
#
# Simple examples to illustrate what some instructions do.
#
# Assuming $9 = 23
addi $8, $9, 1
# $8 <- 24
# Assuming $9 = 23
addi $8, $9, -1
# $8 <- 22
# Assuming $9 = 23
addi $8, $9, 0x12345 # ASSEMBLER SHOULD REJECT THIS INSTRUCTION.
# No result because no such instruction exists.
# Assuming $9 = 0x12345678
andi $8, $9, 0xff # Called a "mask" operation.
# $8 <- 0x78
# Assuming $9 = 23
slti $8, $9, 20 # if( $9 < 20 ) $8 = 1; else $8 = 0;
# $8 <- 0
slti $8, $9, 30
# $8 <- 1
# Assuming $9 = 1
sll $8, $9, 1
# $8 <- 2
sll $8, $9, 3
# $8 <- 8
# Assuming $9 = 16
srl $8, $9, 1
# $8 <- 8
srl $8, $9, 3
# $8 <- 2
sra $8, $9, 1
# $8 <- 8
sra $8, $9, 3
# $8 <- 2
# Assuming $9 = -1 = 0xffffffff
srl $8, $9, 1
# $8 <- 2147483647 = 0x7fffffff
srl $8, $9, 3
# $8 <- 536870911 = 0x1fffffff
sra $8, $9, 1
# $8 <- -1 = 0xffffffff
sra $8, $9, 3
# $8 <- -1 = 0xffffffff
# Assuming $9 = -7 = 0xfffffff9
srl $8, $9, 1
# $8 <- 2147483644 = 0x7ffffffc
srl $8, $9, 3
# $8 <- 536870911 = 0x1fffffff
sra $8, $9, 1
# $8 <- -4 = 0xfffffffc
lui $8, 0x1234
# $8 <- 0x12340000
## Uses for Immediates
#
# Register Initialization
# Constants
# :Example:
#
# Register initialization examples.
#
# Simplified assembler for the following line of C:
#
# a = 23;
# b = 105;
# c = 0x1234a678; // Sixteen bits not enough.
# d = 0;
#
# Asm regs: a, $8; b, $9; c, $10; d, $11
addi $8, $0, 23 # a = 23
addi $9, $0, 105 # b = 105
lui $10, 0x1234 # c = 0x12340000 (so far)
ori $10, $10, 0xa678 # c = 0x1234a678
add $11, $0, $0 # d = 0 (lots of ways to do this)
#
####
# :Example:
#
# Simplified assembler for the following line of C:
#
# rs = ( ir >> 21 ) & 0x1f;
#
# Asm regs: rs, $8; ir, $9.
srl $8, $9, 21
andi $8, $8, 0x1f
####
################################################################################
## Instruction Coding
# :PH: 3.4
# :Mv1: 4.2
## The Three MIPS Instruction Formats
#
# R Format: Typically used for three-register instructions.
# I Format: Typically used for instructions requiring immediates.
# J Format: Used for jump instructions (not covered yet).
#
# Every integer MIPS instruction is in one of these formats.
## R Format
# _________________________________________________________________
# | opcode | rs | rt | rd | sa | function |
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
# 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
#
# Bits Field Name Unabbreviated Name Typical Use
#
# 31:26: opcode First part of opcode.
# 25:21: rs (Register Source) Source register one.
# 20:16: rt (Register Target) Source register two.
# 15:11: rd (Register Destination) Destination register.
# 10:6: sa (Shift Amount) Five-bit immediate.
# 5:0 function Second part of opcode.
#
## I Format
# _________________________________________________________________
# | opcode | rs | rt | immed |
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
# 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
#
# Bits Field Name Unabbreviated Name Typical Use
#
# 31:26: opcode Entire opcode (for I and J).
# 25:21: rs (Register Source) Source register one.
# 20:16: rt (Register Target) Source register two.
# 15:0: immed (Immediate) Immediate value.
## J Format
# _________________________________________________________________
# | opcode | ii |
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
# 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
#
# Bits Field Name Unabbreviated Name Typical Use
#
# 31:26: opcode Entire opcode (for I and J).
# 25:0: ii (Instruction Index) Part of jump target.
## Field Values
#
# Values for fields can be found in the following places:
# :PH: Page A-55 on (2nd edition) Listed by instruction.
# :Mv2: Listed by instruction. "Official" MIPS documentation.
#
# opcode, function
#
# Determined by the instruction.
# For R-format instructions opcode is limited to a few values: e.g., 0, 1.
# The function field takes on a larger range of values.
#
# Values for opcode and function can be found in the following places:
# :PH: Figure A.19 (page A-54) Compact, but perhaps intimidating at first.
# :PH: Page A-55 on (2nd edition) Listed by instruction.
# :Mv2: Listed by instruction. "Official" MIPS documentation.
#
#
# rs, rt, rd
#
# Usually register numbers represented using 5-bit unsigned integers.
# Occasionally used as part of opcode or to specify something other
# than a register.
#
#
# sa (Shift Amount)
#
# A 5-bit constant usually used by shift instructions.
#
#
# immed
#
# A 16-bit quantity.
#
#
# ii (Instruction Index)
#
# A 26-bit quantity used to form a jump target address.
## R Format Examples
# _________________________________________________________________
# | opcode | rs | rt | rd | sa | function |
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
# 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
#
# :Syntax: ADD rd, rs, rt
add $2, $3, $4
#
# Based on the instruction above:
# rd -> 2, rs -> 3, rt -> 4
#
# Using something in :PH: Appendix A or looking up the instruction in :Mv2:
# opcode -> 0, function -> 0x20, sa -> 0
#
# Machine code for the instruction above:
# 0 3 4 2 0 0x20 (By field, each field in hexadecimal)
# = 000000 00011 00100 00010 00000 100000 (By field, binary)
# = 0000 0000 0110 0100 0001 0000 0010 0000 (Groups of four bits)
# = 0x00641020 (Hexadecimal)
#
#
# :Syntax: SLL rd, rt, sa # Shift Left Logical
sll $2, $3, 4
# Based on the instruction above:
# rd -> 2, rt -> 3, sa -> 4
#
# Using something in :PH: Appendix A or looking up the instruction in :Mv2:
# opcode -> 0, function -> 0, rs -> 0
#
# Machine code for the instruction above:
# 0 0 3 2 4 0 (By field, each field in hexadecimal)
# = 000000 00000 00011 00010 00100 000000 (By field, binary)
# = 0000 0000 0000 0011 0001 0001 0000 0000 (Groups of four bits)
# = 0x00031100 (Hexadecimal)
#
## I Format Examples
# _________________________________________________________________
# | opcode | rs | rt | immed |
# ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
# 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
# 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
#
# :Syntax: ORI rt, rs, immed
ori $2, $3, 4
#
# Based on the instruction above:
# rt -> 2, rs -> 3, immed -> 4
#
# Using something in :PH: Appendix A or looking up the instruction in :Mv2:
# opcode -> 13
#
# Machine code for the instruction above:
# 0xd 3 2 4 (By field, each field in hexadecimal)
# = 001101 00011 00010 0000000000000100 (By field, binary)
# = 0011 0100 0110 0010 0000 0000 0000 0100 (Groups of four bits.)
# = 0x34620004 (Hexadecimal)
#
################################################################################
## Pseudo Instructions
# :PH: 3.9 (Briefly under assembler heading.)
# A.K.A. Synthetic Instructions
# :Def: Pseudo Instruction
#
# An assembly language instruction that does not (necessarily)
# correspond to a machine language instruction. The assembler will
# substitute one or two real machine instructions. Pseudo instructions
# are intended to make assembler code more readable and to support
# future ISA extensions. (Some pseudo instructions may become real
# instructions.)
#
# When these notes are viewed in HTML or with the class Emacs package,
# pseudo instructions (those recognized by the SPIM simulator) will be
# italicized. See examples.
## Some Pseudo Instructions
#
# This is not a complete list of pseudo instructions.
#
# (Note: the examples show both pseudo and real instructions. In
# actual assembly code you would use one or the other.)
#
# :Syntax: NOP # No Operation
#
# A special NOP instruction is not needed because many instructions
# will do nothing if register zero is used as the destination.
# Instruction sll is the "official" NOP because its coding is all
# zeros.
#
nop # Pseudo
sll $0, $0, 0 # Real.
#
# :Syntax: MOVE rd, rs # Move
# rd <- rs
#
move $1, $2 # Pseudo
addu $1, $0, $2 # Real
#
#
# :Syntax: LA rd, imm32 # Load Address
# :Syntax: LI rd, imm32 # Load Integer
# rd <- imm32
# Note: SPIM resolves la and li into the same instructions.
# (That is, they do the same thing. Use the one that better
# conveys intent to the human assembly code reader.)
#
#
li $2, 0x12345678 # Pseudo
lui $1, 0x1234 # Real (First of two.)
ori $2, $1, 0x5678 # Real (Second of two.)
li $2, 0x12 # Pseudo
ori $2, $0, 0x12 # Real (Assembler realizes lui not needed.)
################################################################################
## Types of Control-Transfer Instructions
# :PH: Material covered in a different order.
# :Mv1: 4.1.3 (Brief overview.)
## Types of Control Transfers
#
# Branch
# Used for loops, ifs, etc. Most commonly used CTI.
# Instruction specifies a condition and an address, the target.
# If condition is true continue execution at target.
#
# Branch-and-Link
# Used for procedure calls.
# Instruction specifies a condition and an address, the target.
# If condition is true save PC in $31 and continue execution at target.
#
# Jump
# Used for returns and other purposes.
# Instruction specifies a target
# Continue execution at target.
#
# Jump-and-Link
# Used for procedure calls and returns and other purposes.
# Instruction specifies a target
# Save PC in $31 and continue execution at target.
#
# Trap (Not covered in detail in this set.)
# If condition true continue at specified entry in OS-prepared trap table.
#
#
## Conditions and Targets
#
# The methods used to specify conditions and targets vary by instruction.
# See descriptions in following sections
## Delayed CTI <- PAY ATTENTION TO THIS.
#
# All of the CTIs covered here are delayed (except traps).
#
# The instruction after an ordinary delayed CTI IS ALWAYS EXECUTED.
#
add $8, $0, $0
j FORJOY
addi $8, $8, 1
addi $8, $8, 2
FORJOY:
addi $8, $8, 4
addi $8, $8, 8
################################################################################
## A Simple Jump Instruction
# :PH: 3.5
# :Mv2:
# Simple jump (j) covered here, others (jr,jal,jalr) covered in a
# later selection.
# Assembler :Syntax: J target
# Coding :Syntax: J ii
# After next instruction go to { PC[31:28], ii, 2'b0 },
# where ii is bits 27:2 of target.
#
# In assembly language "target" is the line label for the target.
# In machine language "target", the ii field, is bits 27:2 of the
# target address.
# Bits 31:28 of the target address must match bits 31:28 of the jump
# instruction's address. (If not, use the jr instruction.)
# :Example:
#
# Code used to illustrate how target is determined.
FIRSTLINE: # Address of add: 0x400000
add $8, $0, $0
j FORJOY
addi $8, $8, 1
addi $8, $8, 2
FORJOY: # Address of addi: 0x400010
addi $8, $8, 4
addi $8, $8, 8
# In the code above:
#
# FORJOY is a line label, part of the assembly language.
# Suppose the assembler [really the linker] sets FORJOY = 0x400010
################################################################################
## A Branch Instruction
# :PH: 3.5
# :Mv2:
# One branch instruction covered here (bne), others (beq, bltz, etc.)
# covered in a later section.
# Assembler :Syntax: BNE rs, rt, target # Branch Not Equal
# Coding :Syntax: BNE rs, rt, offset
# if rs != rt, after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
#
# "target" is the line label to continue at.
# "offset" is the number of instructions to skip, starting at
# the instruction after the branch.
# :Example:
#
# Code to illustrate the offset.
FIRSTLINE:
add $9, $0, $0
addi $10, $9, 1
bne $9, $10, LINE
addi $8, $8, 1 # Offset computed from this instruction.
addi $8, $8, 2
LINE:
addi $8, $8, 4 # The branch target, offset = 2 instructions.
addi $8, $8, 8
# :Example:
#
# Use of a branch in a loop.
add $8, $0, $0 # $8 -> 0
addi $9, $0, 10 # $9 -> 10
add $10, $0, $0 # $10 -> 0 (i)
LOOP:
add $8, $8, $10 # $8 = $8 + i
addi $9, $9, -1
bne $9, $0, LOOP
addi $10, $10, 1 # i = i + 1
################################################################################
## More Branch Instructions
# :PH: 3.5
# :Mv2:
# Assembler :Syntax: BEQ rs, rt, target # Branch Equal
# Coding :Syntax: BEQ rs, rt, offset
# if rs == rt after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
#
# Assembler :Syntax: BGEZ rs, target # Branch >= Zero
# Coding :Syntax: BGEZ rs, offset
# if rs >= 0 after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
#
# Assembler :Syntax: BGTZ rs, target # Branch > Zero
# Coding :Syntax: BGTZ rs, offset
# if rs > 0 after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
#
# Assembler :Syntax: BLEZ rs, target # Branch <= Zero
# Coding :Syntax: BLEZ rs, offset
# if rs <= 0 after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
#
# Assembler :Syntax: BLTZ rs, target # Branch < Zero
# Coding :Syntax: BLTZ rs, offset
# if rs < 0 after next instruction
# go to PC + 4 + 4 * sign_extend(offset)
################################################################################
## More Jump Instructions
# :PH: 3.5
# :Mv2:
# Assembler :Syntax: JAL target # Jump and link.
# Coding :Syntax: JAL ii
# $31 <- PC + 8
# After next instruction go to { PC[31:28], ii, 2'b0 },
# where ii is bits 27:2 of target.
# Note: $31 a.k.a. $ra
#
# :Syntax: JR rs # Jump register.
# After next instruction go to address in rs.
#
# :Syntax: JALR rs # Jump and link register.
# $31 <- PC + 8
# After next instruction go to address in rs
# Note: $31 a.k.a. $ra
#
# :Example:
#
# Use of j instruction.
# Jump to LINEX
j LINEX
nop
nop
LINEX:
addi $t2, $t2, 1
# :Example:
#
# Use of jal instruction.
LINEA: # LINEA = 0x12345678
# Instruction below is stored at (PC=) 0x12345678
# Set $ra -> PC + 8 = 0x12345680 and jump to LINEX
jal LINEX
nop
nop
LINEX:
addi $t2, $t2, 1
# :Example:
#
# Use of jr instruction.
# Load the address of a line into $to.
la $t0, LINEX
lui $t0, hi(LINEX)
ori $t0, $t0, lo(LINEX)
# Jump to the line.
jr $t0
nop
nop
LINEX:
addi $t2, $t2, 1
# :Example:
#
# Use of jalr instruction.
LINEA: # LINEA = 0x12345678
la $t0, LINEX # Note: this resolves to two instructions.
# Instruction below is stored at (PC=) 0x1234