| Page 1, EE 4720 Lecture Notes Set 9 | Top Previous Next |
Pipelined v. non-pipelined execution units
Initiation interval and latency
Placement in Chapter-3 DLX pipeline
Timing diagrams
| Page 2, EE 4720 Lecture Notes Set 9 | Top Previous Next |
E.g., in DLX second of two consecutive FP divides must stall because of hazard.
(MEM can normally accommodate only one instruction.)
... long before a preceding instruction raises an exception.
| Page 3, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... by duplicating or fully pipelining functional units.
Otherwise, instructions must be stalled.
Hazard easily detected:
Instruction stalled if ready-next-cycle for needed unit is 0.
| Page 4, EE 4720 Lecture Notes Set 9 | Top Previous Next |
Each cycle the reservation register is shifted.
A 1 indicates a "reservation" to enter MEM.
Bit position indicates time ...
... with the LSB indicating two cycles later ...
... the next bit indicating three cycles later ...
... and so on.
The ID stage controller, based on the opcode of the instr., ...
... knows the number of cycles before MEM will be entered.
It checks the corresponding reservation register bit ...
... if it's 1 then IF and ID are stalled ...
... if it's 0 then the bit is set to 1 and the instruction proceeds.
If such a stall occurs ...
... the reservation register is still shifted ...
... and so a 0 will eventually move into the bit position.
| Page 5, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... indicating when it has an instruction ready to enter MEM.
One of those signals is chosen (using some method) ...
... the corresponding instruction moves to MEM ...
... while the others are stalled.
| Page 6, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... since logic remains in one stage.
In contrast, logic for method 2 would span several stages ...
... since stages back to IF might need to be stalled ...
... and so critical paths would be long.
Method 2 is more flexible ...
... since priority could be given to longer-latency instructions.
| Page 7, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... must keep track of registers with pending writes ...
... and use this information to stall instructions.
Consider, add f1, f2, f3.
f2 or f3.If so, stall until register(s) written or can be bypassed to adder.
| Page 8, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... for pending write to register.
Each stage of every pipelined unit must be checked.
Too expensive.
When instruction issued, bit set to 0 ...
... when instruction completes and result written, set back to 1.
Instruction stalls if either operand's ready bit is 0 ...
... and cannot be bypassed.
| Page 9, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... will also handle those WAW hazards ...
... in which there is an intervening write.
If there is no intervening write ...
... the earlier instruction is nulled.
| Page 10, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... so some registers must be unwritten ...
... so that when handler starts ...
... it must seem as though ...
... all instructions before faulting instructions executed ...
... while no instructions after faulting instruction execute.
To do this either ...
... add lots of stalls so instructions do finish in order ...
... or need to unexecute instructions.
The first option is fine for debugging, too slow otherwise.
The second option requires lots of hardware.
| Page 11, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... by restoring the previous contents of any register it wrote.
Method 1: History File
These are used to undo writes.
| Page 12, EE 4720 Lecture Notes Set 9 | Top Previous Next |
... are first placed in a buffer ...
... possibly out of program order.
Writes from buffer to register file performed in order ...
... waiting for long-latency operations to complete.
Register reads check the buffer first, then the register file.
When an exception occurs ...
... only writes preceding the faulting instruction ...
... are made from the buffer to the register file.
Disadvantage: Checking both buffer and register file is time-consuming.
| Page 13, EE 4720 Lecture Notes Set 9 | Top Previous Next |
Future file written as instruction complete ...
... main file written in program order.
Future file is used for reading registers.
At an exception, ...
... main file updated up to faulting instruction ...
... future file is effectively erased ...
... its contents replaced by main register file before handler starts.
| Page 14, EE 4720 Lecture Notes Set 9 | Top Previous Next |
There are other ways of providing precise exceptions.
Functional units can be designed so that ...
... if there will be an exception ...
... it will happen early. (E.g., check for zero divisor.)
With such functional units ...
... it can be determined that instructions are committed ...
... soon after they enter the functional unit.
In this method, stall instructions ...
... until all preceding instructions are committed.
| David M. Koppelman - koppel@ee.lsu.edu | Modified 11 Mar 1998 16:30 (22:30 UTC) |