The book uses "exception" as a general term for all interrupts ...
... in these notes interrupt is used as the general term ...
... and a narrower definition is used for exception.
The definitions of trap, interrupt, and exception given here ...
... are not explicitly provided in the text ...
... but are widely used.
Operating system "takes over" computer ...
... attends to whatever caused the interrupt ...
... and (most of the time) resumes interrupted program.
The OS program that "takes over" in response to interrupt.
Privileged Mode
A state in which the CPU controller and memory system ...
... do not restrict instructions that can be executed ...
... or memory that can be accessed.
Processor switches into privileged mode in response to interrupt ...
... and out of privileged mode when resuming the program.
Sort of a subroutine call to OS.
Something went wrong, triggered by an executing instruction.
Exception has both a general and this specific meaning.
Something is trying to get the computer's attention.
Interrupt has both a general and this specific meaning.
Initiated by a special trap instruction in user code.
Trap causes branch to OS code and a switch to privileged mode ...
... in which there are fewer restrictions on access to memory and I/O.
Typically used for I/O, memory allocation, etc.
Example:
addi r1, r2, r0 ! Place something in r1 preparing for trap. trap ! Call trap routine. (Perhaps to perform IO) sub r5, r6, r7 ! Continue with program.
Called the faulting instruction
Some Exception Causes
... OS either fixes problem and re-tries instruction ...
... or terminates program.
Exceptions frequently occur in the middle of an instruction ...
... which has to be re-started when the program resumes.
Example:
add r1, r2, r3 ! Compute address. lw r6, 0(r1) ! Load data. (May encounter page fault.) sub r5, r6, r7 ! Use loaded data.Here,
lw may generate a page-fault exception.
If so, page fault handler starts after add finishes.
When handler returns, execution resumes with lw
(its second try).
... which typically needs routine attention.
For example,
add r1, r2, r3 sub r4, r5, r6 xor r7, r8, r9As execution reaches code above, achoooo (user sneezes) ...
... moving mouse, triggering an interrupt.
Based on time of sneeze, hardware completes add and sub ...
... but abandons xor (not forever!).
The handler starts ...
... the screen pointer (the little arrow) is moved ...
... the handler finishes ...
... and execution resumes with xor.
All Interrupts: Ability to resume execution as though nothing happened.
Precise Exception: Last instruction must immediately precede faulting instruction.
... because it's hard to stop a pipeline in the middle of something ...
... and have it resume again later ...
... as if nothing happened.
... and abandons all following instructions.
... instructions following last are abandoned (nullified).
trap instruction is inserted in pipe by hardware ...
... which jumps to handler (OS code) and switches to privileged mode.
... with the instruction following last.
... while instructions following the last must have no effect at all ...
... even though they may have already started when the interrupt occurred.
These abandoned instructions will be executed after the handler completes.
No problem.
No problem again.
Problem: exception can occur in any of several stages.
Problem: more than one instruction can raise exception.
Problem: an instruction can raise exception before its predecessor.
Problem: despite problems, some exceptions must be precise.
When the handler finishes and the program resumes ...
... it must be as though the abandoned instructions never even started.
So ...
... they cannot write registers ...
... they cannot write memory ...
... or set any kind of condition codes ...
... unless ...
... the state change can be un-done.
... because they change state in the last two stages (MEM & WB).
To abandon an instruction in the IF, ID, or EX stages ...
... the opcode is replaced with a NOP ...
... or any control bits that initiate a memory or register write ...
... are set to perform no action.
An instruction in WB cannot easily be abandoned ...
... because the following instruction, in MEM, ...
... would already be changing state.
Fortunately, there's never a need to abandon an instruction in WB ...
... although an already-abandoned instruction can enter WB.
An instruction in MEM cannot be abandoned ...
... unless the memory operation fails ...
... which, luckily, is the only reason to abandon the instruction.
ID: Illegal opcode, detected by decode logic.
EX: Arithmetic exception, detected by ALU.
MEM: Page fault on load/store, detected by memory port.
If exception occurs, written with exception info.
If exception register non-null ...
... exception info, PC, and other information copied somewhere ...
... and trap instruction placed in IF stage of pipeline.
... and abandons all following instructions ...
... handler must arrange things so execution can resume where it left off.
trap instruction is inserted in pipe by hardware ...
... which jumps to handler (OS code) and switches to privileged mode.
... handler may have to ...
... determine which instructions finished ...
... and which were in progress.
... an interrupted instruction can resume in the middle.
... and expensive for others.
They are necessary for instructions ...
... such as memory loads and stores.
For other instructions they are a convenience ...
... for example FP instructions ...
... that can write error values instead of numbers ...
... if they don't complete.
In many systems precise exceptions are optional for floating point ...
... but always provided for other instructions.
| David M. Koppelman - koppel@ee.lsu.edu | Modified 5 Mar 1998 15:31 (21:31 UTC) |