EE 4720 Lecture Notes

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               Instruction Set (ISA) Design and Addressing Modes


       To be covered:


        -  ISA Design Overview (2.1)


        -  Architecturally visible storage.


        -  ISA classification based on register organization.  (2.2)


        -  Addressing modes.  (2.3)


        -  Impact on ISA.



03-1                      EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.*
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03-2 * * 03-2 ISA Design Overview ISA Design Choices (In reverse order.) - Instruction Operations (ADD, SUB, etc.) - Instruction Forms and Coding (number of operands, etc.) - Specifying Operands (we'll get into that) Instruction Operations - Arithmetic and Logical Instructions You know, ADD, MUL, XOR. - Control Transfer Collective term for branches, jumps, and subroutine calls. - Data Movement (Load/Store, Register Movement) Includes, register $ register, register $ memory, memory $ memory. - Process Management (Operating System, etc.) For use by OS to control interaction of programs. 03-2 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-2
03-3 * * 03-3 Specifying Operands: Architecturally Visible Storage Consider: ADD hsum i = hop1 i + hop2 i Operands hop1 i and hop2 i can refer to: - A Constant - Something Written Earlier Since "Something Written Earlier" is part of instruction : : : : : :the ISA must define names for that storage. Since storage defined by ISA it's called architecturally visible storage. Common types of architecturally visible storage: - Registers Sometimes there are multiple sets. - Memory Sometimes there are multiple address spaces. Other types are less common. What ISA Defines for Architecturally Visible Storage - Names. For registers, r1, f30, g6. For memory, 53023. - Result of writing and reading storage. Not obvious with multiple readers and writers. 03-3 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-3
03-4 * * 03-4 Registers and Memory Registers (Internal Storage) Store what is actively being worked on. E.g. Math expression parts, array indices. Implemented using highest speed memory. Given short names. E.g. r1, g1, AL. Small number of registers provided. E.g. 32, 64. Goal: fastest access. Memory Stores code and data. Simple to programmer : : :despite complex implementation. Large number of locations, 232 = 4294967296 and 264 = 18446744073709551616 are common. Named using integers called addresses: : : : : :and some address space identifier. Goal: large size. 03-4 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-4
03-5 * * 03-5 Specifying Operands: ISA Classification Consider: ADD hsum i = hop1 i + hop2 i What hop1 i and hop2 i usually refer to: - Register contents. - Memory contents. - Part of instruction. - A constant. ISAs classified on allowable register and memory operands. 03-5 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-5
03-6 * * 03-6 ISA Classification Classified by allowed register and memory operands. Listed below by distinguishing features : : : : : :and intended (contemporary) benefits. Next slide: current relevance. Load/Store, General-Purpose Registers (GPR) ALU instructions refer only to registers. (Not memory.) Memory $ register movement uses Load and Store instructions. Number of special-purpose registers minimized. )Keep memory and ALU operations separate. )Avoid special-purpose instructions. Memory/Memory, General-Purpose Registers Both load/store instructions and ALU instructions : : : : : :can refer to both registers and memory. Few special-purpose registers. )Use registers only when needed. 03-6 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-6
03-7 * * 03-7 Accumulator Typical ALU instruction uses: : : : : :a special accumulator register: : : : : :and a general purpose register. Only the general purpose register need be specified. )Keep instructions small. Stack Instructions to push and pop data from stack. ALU instructions refer to stack. No registers in usual sense. )Natural way to evaluate expressions. 03-7 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-7
03-8 * * 03-8 Tradeoffs of ISA Types Load/Store, General-Purpose Registers (GPR) Used in most ISAs developed in past decade. + Programmer- and compiler-friendly. (Since most registers can be used for any purpose.) + Allow single-size instruction coding. (Since multiple memory addresses not needed in ALU instr.) Memory/Memory, General-Purpose Registers + Lots of addressing options for programmers. - Lots of addressing options forces slower implementation. Accumulator - Extra instructions needed to move data. Stack + Programs small. - Implementations slow. - Hard to code certain expressions. 03-8 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-8
03-9 * * 03-9 Common Addressing Modes Addressing modes used by many ISAs. Register Data in register. Move R4, R3 ! R4 = R3 (This is a comment.) Immediate Data in instruction. Move R4, #3 ! R4 = 3 Register Deferred or Register Indirect Data address in register. Load R4, (R1) ! R4 = MEM[R1] Displacement Data address is register plus constant. Load R4, 100(R1) ! R4 = MEM[ R1 + 100 ] Indexed Data address is sum of two registers. Load R4, (R1+R2) ! R4 = MEM[ R1 + R2 ] Direct Data address is a constant. Load R1, (1024) ! R1 = MEM[ 1024 ] 03-9 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03.* * 03-9
03-10 * * 03-10 Memory Indirect Address of data's address is in register. Load R1,@(R3) ! R1 = MEM[ MEM[ R3 ] ]. Autoincrement Perform register indirect access, then add constant to register. Load R1,(R2)+ ! R1 = MEM[ R2 ]; R2 = R2 + 1 Autodecrement Subtract constant from register then perform register indirect access. Load R1,-(R2) _ R2 = R2 - 1; R1 = MEM[ R2 ]; Scaled Data address is constant1 + reg1 + reg2 * constant2. Load R1,100(R2)[R3] ! R1 = MEM[ 100 + R2 + R3 d ] There's no limit to how many addressing modes one could think of. 03-10 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-10
03-11 * * 03-11 Memory Addressing Choices in ISA Design Which addressing modes? Affects cost and may limit future performance. Which instructions get which addressing modes? Affects cost and may limit future performance. Maximum displacement size? Limited by instruction size. Maximum immediate size? Limited by instruction size. 03-11 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-11
03-12 * * 03-12 Usage of Addressing Modes Do we really need all those addressing modes? Memory Addressing Usage in VAX Code. VAX uses all of addressing modes described earlier. Modes used less than 1% of time omitted. Large differences between programs. Since a few modes account for most accesses : : : : : :others could be omitted with little impact on performance : : : : : :saving silicon area (but programs would have to be rewritten). 03-12 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-12
03-13 * * 03-13 Displacement Sizes What should the maximum displacement size be? Too large: difficult to code instruction. Too small: won't be very useful. Displacement Size in SPECint92 and SPECfp92 Programs on MIPS. Wide range of displacements used. 03-13 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-13
03-14 * * 03-14 Immediate Sizes What should the maximum immediate size be? Too large: difficult to code instruction. Too small: won't be very useful. Immediate Sizes in VAX Code Smaller values used more frequently. 03-14 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-14
03-15 * * 03-15 Internal Storage Variations Operands per Instruction Three typically used. Two sometimes used. Factors: Instruction coding (bits to specify operands). Addresses per ALU Instruction Zero typically used (load/store). One, two, even three sometimes. Factors Instruction coding. (Addresses take up lots of space.) Benefit over multiple instructions. 03-15 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-15
03-16 * * 03-16 Memory Addressing Address Interpretation Sequence of memory locations (usually bytes) starting at address. Size of sequence depends upon instruction. E.g., LW, load word instruction might read four bytes. E.g., LB, load byte instruction might read one byte. Alignment Addresses subject to alignment restrictions: : : : : :when used in certain instructions. E.g., a word-aligned address must be divisible by 4 (usual word size). 03-16 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-16
03-17 * * 03-17 Past Choices Vax (Digital Equipment Corporation) Older ISA, variable instruction size. Provides many addressing modes usable by many instructions. Instructions use 32-bit immediate. + (ISA) Compact code. - (Imp) Future implementations limited. So limited that DEC developed a new ISA, Alpha. - (Imp) Expensive-to-implement modes go unused. SPARC V8 (Sun Microsystems) Newer ISA, fixed 32-bit instruction size. Load/Store instruction modes: indexed and 13-bit displacement. ALU instruction modes: register and 13-bit immediate. sethi instruction modes: 22-bit immediate. (Used for moving large immediate into registers.) + (Imp) Uniform instruction sizes. + (Imp) Useful modes included. 03-17 EE 4720 Lecture Transparency. Formatted 19:35, 11 March 1998 from lsli03* *. 03-17

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Modified 11 Mar 1998 19:35 (1:35 UTC)