/// LSU EE 3755 -- Fall 2012 -- Computer Organization // /// Code by end of class 9 November 2012. // /// Hardwired Control, Multicycle MIPS, Day 1 // // Will be added to each day. // `define MIPS_PROG "uc.v" module cpu(exc,data_out,addr,size,we,data_in,mem_error_in,reset,clk); input [31:0] data_in; input [2:0] mem_error_in; input reset,clk; output [7:0] exc; output [31:0] data_out, addr; output [1:0] size; output we; reg [31:0] data_out, addr; reg [1:0] size; reg we; reg [7:0] exc; // MIPS Registers // reg [31:0] gpr [0:31]; reg [31:0] pc, npc; reg [31:0] ir; // Instruction Fields // reg [4:0] rs, rt, rd, sa; reg [5:0] opcode, func; reg [25:0] ii; reg [15:0] immed; // Values Derived From Immediates and Read From Register File // reg [31:0] simmed, uimmed, limmed; reg [31:0] rs_val, rt_val, sa_val; reg [75:0] bndl; // ALU Connections // // Values for the MIPS funct field. // parameter F_sll = 6'h0; parameter F_srl = 6'h2; parameter F_add = 6'h20; parameter F_sub = 6'h22; parameter F_or = 6'h25; // Values for the MIPS opcode field. // parameter O_rfmt = 6'h0; parameter O_j = 6'h2; parameter O_beq = 6'h4; parameter O_bne = 6'h5; parameter O_addi = 6'h8; parameter O_slti = 6'ha; parameter O_andi = 6'hc; parameter O_ori = 6'hd; parameter O_lui = 6'hf; parameter O_lw = 6'h23; parameter O_lbu = 6'h24; parameter O_sw = 6'h2b; parameter O_sb = 6'h28; // Processor Control Logic States // // ALU Operations // parameter OP_nop = 6'd0; parameter OP_sll = 6'd1; parameter OP_srl = 6'd2; parameter OP_add = 6'd3; parameter OP_sub = 6'd4; parameter OP_or = 6'd5; parameter OP_and = 6'd6; parameter OP_slt = 6'd7; parameter OP_seq = 6'd8; // Handy Constant // parameter R0 = 5'd0; alu our_alu(alu_out,alu_a,my_alu_b, our_alu_op); alu our_other_alu(alu_out2,alu_a2,my_alu_b2, our_alu_op2); always @ ( posedge clk ) begin F_add: // gpr[rd] = gpr[rs] + gpr[rt]; alu_a = gpr[rs]; end endmodule module alu(alu_out,alu_a,alu_b,alu_op); output [31:0] alu_out; input [31:0] alu_a, alu_b; input [5:0] alu_op; reg [31:0] alu_out; // Control Signal Value Names parameter OP_nop = 0; parameter OP_sll = 1; parameter OP_srl = 2; parameter OP_add = 3; parameter OP_sub = 4; parameter OP_or = 5; parameter OP_and = 6; parameter OP_slt = 7; parameter OP_seq = 8; always @( alu_a or alu_b or alu_op ) case( alu_op ) OP_add : alu_out = alu_a + alu_b; OP_and : alu_out = alu_a & alu_b; OP_or : alu_out = alu_a | alu_b; OP_sub : alu_out = alu_a - alu_b; OP_slt : alu_out = {alu_a[31],alu_a} < {alu_b[31],alu_b}; OP_sll : alu_out = alu_b << alu_a; OP_srl : alu_out = alu_b >> alu_a; OP_seq : alu_out = alu_a == alu_b; OP_nop : alu_out = 0; default : begin alu_out = 0; $stop; end endcase endmodule // exemplar translate_off module system(exc,reset,clk); input reset,clk; output [7:0] exc; wire [31:0] cpu_data_out, addr, mem_data_out; wire [2:0] mem_err_out; wire [1:0] size; wire we; cpu cpu1(exc,cpu_data_out,addr,size,we,mem_data_out,mem_err_out,reset,clk); mips_memory_1p m1(mem_data_out,mem_err_out,addr,size,we,cpu_data_out,clk); endmodule `include "mips_hc_tb.v"