/// LSU EE 3755 -- Computer Organization -- Spring 2002
//
// Verilog code example: log_eq

// Output, x, 1 if a equals b.

module log_eq(x,a,b);
   input [1:0] a, b;
   output x;

   //  assign x = a == b; // This is the easy way to do it.

   wire   x1, x2;

   xnor xor0(x1,a[0],b[0]);
   xnor xor1(x2,a[1],b[1]);

   and a1(x,x1,x2);

endmodule