/// LSU EE 3755 -- Fall 2001 -- Computer Organization
//
/// Spring 2002 Final Exam Review
// Time-stamp: <10 May 2002, 11:51:18 CDT, koppel@sol>
/// Contents
//
// Exam Format
// Exam Topics
// How to Study (Under Construction)
module final_exam();
parameter exam_date = "Thursday, 16 May 2002";
parameter exam_time = "12:30 CDT";
parameter exam_room = "Here, 2150 CEBA";
always @( avaialble_time ) begin
review_basics;
for(h=1; h<=5; h=h+1) solve_homeork(h);
solve_fall_2001_hw_six_and_seven();
solve_midterm();
solve_practice_final();
end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Exam Format
// Allowed one 215 x 280 mm note sheet.
// No communication devices.
/// Possible Problem Types
//
// Given a MIPS implementation, determine what new instruction does.
// Add an instruction to a MIPS implementation.
// Write a MIPS program.
// Show hardware synthesized from Verilog.
// Write Verilog for an illustrated piece of hardware.
// Write Verilog for some arithmetic operation.
// Show timing diagram (like wave window) for Verilog.
// Etc.
////////////////////////////////////////////////////////////////////////////////
/// Exam Topics
/// Verilog
//
// Defining and instantiating a module.
// Module ports and connections.
// Registers and wires.
// Expressions.
// Non-procedural code, continuous assignments.
// initial begin ... end
// always @( posedge foo ) begin ... end blocks.
// always @( foo or bar or foobar ) begin ... end blocks.
/// Synthesis
//
// Form 1: Combinational logic and level-triggered registers.
// Form 2: Edge triggered registers.
// Relationship between procedural code and synthesized hardware.
/// Arithmetic Hardware
//
// Representations, algorithms, and hardware for integer addition and subtr.
// Binary multiplication and division algorithms and hardware.
// High-radix and Booth multiplication algorithms and hardware.
// IEEE 754 Floating Point Representations.
// Floating point arithmetic algorithms.
/// MIPS
//
// Know what instructions do.
// Registers, memory.
// Be able to write programs.
/// MIPS Implementations
//
// MIPS Functional Simulator
// Hardwired MIPS Implementation
////////////////////////////////////////////////////////////////////////////////
/// How to Study
/// Under Construction
module solve_problem(problem);
input [999999:0] problem;
reg [2:0] state;
wire [999999:0] brain_input = problem;
wire [5:0] brain_state;
always @( brain_input_src or problem or motivational_stuff )
case( brain_input_src )
bis_study: brain_input = problem;
bis_mot: brain_input = motivational_stuff;
endcase
parameter bstate_tried = 6'd0;
parameter bstate_confused = 6'bxxxxxx;
parameter bstate_seeing_it = 6'd1;
parameter bstate_got_it = 6'd2;
parameter bstate_lost = 6'd3;
brain my_brain(brain_state,brain_input);
parameter st_start = 1;
reg clk;
always begin clk = 0; #5; clk = 1; #5; end
always @( posedge clk )
case( state )
endcase
endmodule