```/// LSU EE 3755 -- Computer Organization -- Spring 2002
//
// Verilog code example: gt

// Output, x, 1 if a > b; a and b are unsigned integers.

// Module is in explicit structural form.  Because the ">" operator
// is available there is no need to use an explicit structural
// description, "assign x = a > b" would do.

module gt(x,a,b);
input [1:0] a, b;
output      x;

wire        na1, nb1;
not n1(na1,a[1]);
not n2(nb1,b[1]);

wire        lt1, gt1;
and a1(gt1,a[1],nb1);
and a2(lt1,na1,b[1]);

wire        decided1;
or o1(decided1,lt1,gt1);

wire        na0, nb0;
not n3(na0,a[0]);
not n4(nb0,b[0]);

wire        gt0, lt0;
and a3(gt0,a[0],nb0);
and a4(lt0,na0,b[0]);

wire        decided1_and_gt1, not_decided1, not_decided1_and_gt0;
and a5(decided1_and_gt1,decided1,gt1);
not n5(not_decided1,decided1);
and a6(not_decided1_and_gt0,not_decided1,gt0);

or o2(x,decided1_and_gt1,not_decided1_and_gt0);

endmodule

/// Testbench Output
/
// vsim> run -all
// #  0 > 0 == 0
// #  0 > 1 == 0
// #  0 > 2 == 0
// #  0 > 3 == 0
// #  1 > 0 == 1
// #  1 > 1 == 0
// #  1 > 2 == 0
// #  1 > 3 == 0
// #  2 > 0 == 1
// #  2 > 1 == 1
// #  2 > 2 == 0
// #  2 > 3 == 0
// #  3 > 0 == 1
// #  3 > 1 == 1
// #  3 > 2 == 1
// #  3 > 3 == 0

/// Testbench

module testgt();

wire x;
reg [1:0] a, b;

gt my_gt(x,a,b);

integer i;

initial begin

for(i=0; i<16; i=i+1) begin

{a,b}=i[3:0];
#1;

\$display(" %d > %d == %d",a,b,x);

end

end

endmodule
```