```////////////////////////////////////////////////////////////////////////////////
///
/// Solution to LSU EE 3755 Fall 2001 Homework 1
///

/// Name:  David M. Koppelman

/// Instructions:
//
// Copy this to a file named hw01sol.v to directory ~/hw in your
// class account. (~ is your home directory.)  Use this
// this file.
//
// Do not rename the modules in this file and be sure to use the
// directory and filename given above.

// Assignment: http://www.ee.lsu.edu/ee3755/2001f/hw01.pdf

////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
/// Problem 1
///

module hello();

initial begin
\$display("Hello, world!");
end

endmodule

////////////////////////////////////////////////////////////////////////////////
/// Problem 2
///

module eq_slice_es(eo,a,b,ei);
input a, b, ei;
output eo;

wire   aneb, aeqb;

xor x1(aneb,a,b);
not n1(aeqb,aneb);
and a1(eo,aeqb,ei);

endmodule

////////////////////////////////////////////////////////////////////////////////
/// Problem 3
///

module eq_slice(eo,a,b,ei);
input a, b, ei;
output eo;

assign eo = ( a == b ) && ei;

endmodule

////////////////////////////////////////////////////////////////////////////////
/// Problem 4
///

module equal(eq,a,b);
input [3:0] a, b;
output      eq;

wire        e1, e2, e3;

eq_slice es3(e3,a[3],b[3],1'b1);
eq_slice es2(e2,a[2],b[2],e3);
eq_slice es1(e1,a[1],b[1],e2);
eq_slice es0(eq,a[0],b[0],e1);

endmodule

////////////////////////////////////////////////////////////////////////////////
/// Test Bench
///

// Do not remove comment below.
// exemplar translate-off

module test();

reg abit, bbit, ei;
wire eoe, eoi, eq;
reg [3:0] a, b;

eq_slice_es ees(eoe,abit,bbit,ei);
eq_slice eis(eoi,abit,bbit,ei);
equal eqaul1(eq,a,b);

integer   i, es_probs, ei_probs, eq_probs;

initial
begin
es_probs = 0;
ei_probs = 0;
eq_probs = 0;

for(i=0; i<8; i=i+1)
begin

{abit,bbit,ei} = i[2:0];
shadow_eo = ( abit == bbit ) && ei;

#1;

begin
if( !es_probs )
\$display("Problem with eq_slice_es at a = %d, b = %d, ei = %d",
abit, bbit, ei);
es_probs = es_probs + 1;
end

begin
if( !ei_probs )
\$display("Problem with eq_slice at a = %d, b = %d, ei = %d",
abit, bbit, ei);
ei_probs = ei_probs + 1;
end
end

for(i=0; i<256; i=i+1)
begin

{a,b} = i[7:0];

#1;

begin
if( !ei_probs )
\$display("Problem with equal at a = %d, b = %d", a, b);
eq_probs = eq_probs + 1;
end

end

\$display("Done with tests.");
if( eq_probs + es_probs + ei_probs == 0 ) \$display("No problems found.");
end

endmodule
```