EE 4250 - Spring 2006
Title: Digital Integrated Circuit Design
- Catalog Description: Prereq.: EE 3220, 3221, and 3232. 2 hrs. lecture; 2 hrs. lab. ABET category: 2 hrs. design; 1 hr. engineering science. Analysis and design of digital integrated circuit logic gates in bipolar and MOS technology; semiconductor memories and their operations.
- Instructor: Dr. Dooyoung Hah
- Lecture: MW 8:40-9:30, 3142 CEBA
- Lab: T 8:40-10:30 (Mr. Jose Marulanda) / 3:10-5:00 (Dr. Dooyoung Hah), EE252
- Office hour: MW 10:00-11:30 AM, TTH 10:30-11:30 AM
- Textbook: Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, D. A. Hodges, H. G. Jackson and R. A. Saleh, McGraw-Hill, 3rd Edition, 2003.
- Errata of the text book (Under Student Resource)
- You need a password which was provided at the end of the class (2/6) to open the solutions given below. If you haven't got it from me, please ask your classmate.
- Solution of the mid-test1. (pdf)
- Mid-test1 class average = 49.15
- Correction regarding VOL for a saturated enhancement load inverter. (pdf)
- Solution of the mid-test2. (pdf)
- Mid-test2 class average = 66.5
- Home Assignment #1 (pdf, class average = 7.65) ----> solution
- 1-1(b) & 1-2(b): IRflows during storage delay.
- Home Assignment #2 (pdf, class average = 7.91) ----> solution
- For the definition of VIL,VIH, VOL, and VOH, refer to Fig. 4.2 in the textbook (p. 146).
- For the definition of NMH and NML, see Fig. 4.8 in the textbook (p. 152).
- Home Assignment #3 (class average = 28.56) ----> solution
- Home Assignment #4 (pdf, class average = 69.13) ----> revised solution
- Home Assignment #5 (pdf, class average = 32.06) ----> solution
- 5-1: You may use Cout as one of inputs for Sum. You don't have to include inverters for complementary inputs.
- Home Assignment #6 (Due Date - noon, May 10): P6.6, 6.11, and 6.12. ----> solution NEW!
- P6.11 and 6.12: Gate sizing will be sufficient. (You don't have to do the transistor sizing.) NEW!
- P6.12: Use 2 for LE and 3 for P for NAND4. NEW!
- Please turn in your assignment at my office.
- Threshold voltage of NMOS - Band diagrams (pdf)
- Derivation of VDS,sat, saturation drain-source voltage with velocity saturation (pdf)
- A summary table I-V equations of MOS (pdf)
- 2N2222: Philips NPN switching transistor
- 74LS00: Motorola Quad 2-input NAND gate
- CD4001: National Semiconductor Quad 2-input NOR gate
- LM555: National Semiconductor LM555 timer
- LM556: National Semiconductor LM556 dual timer
- BS170: Philips Semiconductors BS170 NMOS
- BS250: Philips Semiconductors BS250 PMOS
SPICE Simulation Guide
- Try the simulation example that CADENCE PSPICE offers.
- Run the CAPTURE CIS under CADENCE PSD 15.1 from the START menu.
- Select MANUAL under the HELP pull-down menu.
- Find and open /PSPICE/PSPICE User's Guide/2.Simulation Examples.
- Follow the instruction.