//This is the part of solution 
//Very simple.
//We will also use this for the synthesizer 
   module neq_slice_es(eo,a,b,ei);

    input a, b, ei;

    output eo;


    wire   aneb, aeqb;

    xor x1(aneb,a,b);

    and a1(eo,aneb,ei);


endmodule



module nequal(eq,a,b);

   input [3:0] a, b;

   output      eq;


   wire        e1, e2, e3;

   neq_slice_es es3(e3,a[3],b[3],1'b1);

   neq_slice_es es2(e2,a[2],b[2],e3);

   neq_slice_es es1(e1,a[1],b[1],e2);

   neq_slice_es es0(eq,a[0],b[0],e1);


endmodule