problem 1: Complete the module
###########################################
module
three_bit_Booth(prod,ready,multiplicand,multiplier,start,clk);
input [15:0] multiplicand, multiplier;
input start, clk;
output prod;
output
ready;
reg [32:0] product;
wire [31:0] prod = product[31:0];
reg [3:0] bit;
wire ready = !bit;
reg d;
initial bit = 0;
wire [16:0] multsx = {multiplicand[15],multiplicand};
always @( posedge clk )
if( ready && start ) begin
bit = 8;
product = { 17'd0, multiplier };
d = 0;
end else if( bit ) begin
//Sol
case (
{product[1:0],d} )
3'b001: product[32:16] = product[32:16] + multsx;
3'b010:
product[32:16] = ##product[32:16] + multsx;
3'b011:
product[32:16] = ##product[32:16] + 2 * multiplicand;
3'b100:
product[32:16] = ##product[32:16] - 2 * multiplicand;
3'b101:
product[32:16] = ##product[32:16] - multsx;
3'b110:
product[32:16] = ##product[32:16] - multsx;
endcase
d = product[1];
product = { product[32], product[32],
product[32:2] };
bit = bit - 1;
end
endmodule
Problem 2: Complete the module.
################################################################
// A 5-bit CLA using
five cla slice parts. The generate and
propagate
// signals are used to
produce the carry signals.
module cla_5(sum,cout,
a,b,cin);
input [4:0] a, b;
input cin;
output [4:0] sum;
output
cout;
wire [4:0] g, p, carry;
/// Logic for Carry Signals
assign carry[0] = g[0] |
cin & p[0];
assign carry[1] = g[1] |
g[0] & p[1] |
cin & p[0] & p[1];
assign carry[2] = g[2] |
g[1] & p[2] |
g[0] & p[1] & p[2] |
cin
& p[0] & p[1] & p[2];
assign carry[3] = g[3] |
g[2] &p[3] |
g[1] &p[2] & p[3] |
g[0] & p[1] & p[2] &p[3] |
cin
& p[0] & p[1] & p[2] & p[3];
assign
carry[4] = g[4] | g[3]
& p[4] |
g[2] & p[3] & p[4] |
g[1] & p[2] & p[3] &
p[4] |
g[0] & p[1] & p[2] &p[3]
& p[4] |
cin
& p[0] & p[1] & p[2] & p[3] & p[4];
//Solution comes here
assign sum[0] = p[0] ^ cin;
assign sum[1]
= p[1] ^ carry[0];
assign sum[2]
= p[2] ^ carry[1];
assign sum[3]
= p[3] ^ carry[2];
assign sum[4]
= p[4] ^ carry[3];
assign cout
= carry[4];
//#####################
cla_slice_part s0(g[0],p[0],a[0],b[0]);
cla_slice_part s1(g[1],p[1],a[1],b[1]);
cla_slice_part s2(g[2],p[2],a[2],b[2]);
cla_slice_part s3(g[3],p[3],a[3],b[3]);
cla_slice_part s4(g[4],p[4],a[4],b[4]);
endmodule
Problem 3: The following module my_loop is not working.
##############################################
module my_loop(a,b);
input [15:0] b;
output a;
reg [3:0] a;
reg [3:0] i;
integer s;
initial begin
s = 0;
for(i=0; i<16; i=i+1)
s = s + a[i];
a = s;
end
endmodule
a) what is wrong with
the above module?
Infinity loop.
And only
count upto 15 0nes..
b) modify the
module as little as possible to make it
working.
hint: it has one 16bits input. This is a
very easy one. You dont have to add any more code.
it should count the number of 1s in the input(b).
change [3:0] => [4:0]
problem 4: module not_synthesizable_sum(sum,a);
########################
input [7:0] a;
output [10:0] sum;
reg [10:0] sum;
integer i;
initial
always @( a ) begin
sum = 0;
for(i=0; i<=a; i=i+1) #3 sum = sum +
i;
end
endmodule:
//Answer the questions
a) the above module is
not synthesizable. Why?(Short answer )
initial
delay
undetermined loop index
Problem 5: Convert the following numbers:
Hint (3/8) = 0.375
a) Decimal 14 to 8-bit Binary:
//00001110
b) Decimal -14 to 8-bit Binary:
// 11110010
c) Decimal 14.375 to Binary (as many
bits as needed):
//1110.011
d) Decimal -14.375 to IEEE 754 Single Precision (Show in
hexadecimal):
Hint : Hidden one
//C1660000
Problem 6: Write a MIPS CODE for the following
line of C:
#
# x = a + b >
( c & mask ) | d;
# regs usage: x, $8; a, $9;
b, $10; mask, $11; c, $12;
# d, $13
Sol)
add $20, $9, $10 # a
+ b
and $21, $12, $11 # c & mask
or $21, $21, $13 # ( c & mask ) | d
slt $8, $21, $20 # ( a + b) > (( c & mask ) | d);
Problem 7:
Write a MIPS CODE for the following line of C:
#
# a = 23;
# b = 105;
# c = 0x1234a678; // offset field Sixteen bits not enough.
# d = 0;
#
# if( a + b > c ) { d = d
>> 1; e++; } else { d = d << 1; e--; }
# i++;
#
# Reg Usage: a, $8; b, $9;
c, $10; d, $11; e, $12;
i, $13
sol)
add $16, $8, $9 # $16 = a + b
slt $17, $10, $16 # $17 = c < a + b
beq $17, $0, ELSEPART
nop
sra $11, $11, 1 # d = d >> 1
addi $12, $12, 1 # e++;
j LINEX
nop
ELSEPART:
sll $11, $11, 1 # d = d << 1
addi $12, $12, -1 # e--
LINEX:
addi $13, $13, 1 # i++
Problem
8: The following instructions are NOT MIPS32 instructions:
SUBI,
NORI #
Implement these instructions by using real
instructions.
SOL)
# subi
$t1,$t2, 0x1234
addi $t1,$t2, -0x1234
#
nori $t1,$t2, 0x1234
addi $t0,$0, 0x1234
nor
$t1, $t0,$t2
Problem 9: Complete the module.
Implement MUL instruction.
#Note: SPIM treats this as a pseudo instruction, but it is
#a real
instruction in MIPS32
Syntax: MUL rd,
rs, rt
# rd <- rs * rt;
implement this pseudo
code with real instructions
# mul $2,
$3, $4 # Pseudo(without overflow)
sol)
mult $3, $4 # Real (First of two.)
mflo $2
.
Problem 10: Write
a MIPS program to print values from register $t1
8 bits at a time.
//Dont panic . You dont have to know how to print.
For example )
$t1 = 0x01020304,
It will print: 1
2
3
4.
You dont
have to write a print routine. USE Print_Sub
subroutine which will print $a0 register value and will return by using $ra register value.
Sol).
.data
item: .asciiz "\n"
.text
.globl __start # Must
be global
__start: add $t1,$0,0x01020304 //for testing purpose
move $a0,$t1
srl $a0,$a0,24
andi $a0,$a0,0x000f
jal PRINT_SUB
nop
move $a0,$t1
srl $a0,$a0,16
andi $a0,$a0,0x000f
jal PRINT_SUB
nop
move $a0,$t1
srl $a0,$a0,8
andi $a0,$a0,0x000f
jal PRINT_SUB
nop
move $a0,$t1
andi $a0,$a0,0x000f
jal PRINT_SUB
nop
addi $v0,$0,10
syscall
PRINT_SUB: addi $v0,$0,1
syscall
jr $ra
nop
Print_Sub : addi $v0, $0,1
syscall
jr $ra
nop #actually this will
print 1234
because there is no new line
Problem 11: the module below is an adder unit.
################
module adder(sum,a);
input [7:0] a;
output [10:0] sum;
reg [10:0] sum;
integer i;
always @( a ) begin
sum = 0;
for(i=0; i<4; i=i+1) if( i <= a )
sum = sum + i;
end
endmodule
What will
be the synthesizer output?
Draw the figure.