MIME-Version: 1.0 Content-Location: file:///C:/B12A0251/HW11_11.htm Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset="us-ascii" EE 3755 Homework 1 Due: 20 October 2003

EE 3755 =         =             &nb= sp;   Homework= 1         =    Due: TBA=

 

Important: When logging in for the first time select “Common Desktop Environment"

after enter= ing your user name and password.

 (If you're reading this after selecting the wrong option, log out and then, from the log in dialog select Options, Session, Common<= /span> Desktop Environment.)

Solve this problem by modifying a copy of  = http://www.ece.lsu.edu/alex/EE3755/2004/hw01.v

 

 <= /p>

 <= /p>

Estimate= d time to finish:

     Knowing How to U= se ncverilog:  1 Min..

     Prob1        =             &nb= sp;            =            :  1Min.

     Prob2        =             &nb= sp;            =            :  10Mins.

     Prob3        =             &nb= sp;            =            :  10Mins.

     Prob4        =             &nb= sp;            =            :  10Mins. <= /span>

     Prob5        =             &nb= sp;            =            :  30Mins.

    Total        =             &nb= sp;            =              :  62 Mins..

    When you submit the Hw., Please write down how much t= ime did you spend for each problem. 

    (No penalty for spendi= ng too little or too much time. Just want to know how long you spent.)<= /span>

  How to submit:  Hard copy during the class.

  Use “script “ command to take a  snap= shot of your program.

Problem = 1: Copy the homework template into a subdirectory named hw in your class account. Simulate the welcome module in the homework template.

The logic diagram below is a 1-bit slice of a circuit that is used to determine whether a=3D~b.

One bit of one integer is put on input a and one bit of the other integer is put on input b.

(If the number has ten bits then ten slices would be needed.) Ports = ei and eo work somet= hing like carry in and carry out in a binary full adder.

 Input ei is logic 1 if the higher bits of the two numbers are not equal. (ahigh=3D~bhigh). Output eo is logic 1 if ei= =3D1 and a=3D~b.

An image:

= The homework template contains module definitio= ns for solutions to the problems below. It

also contains a testbench, called test, that= can be used to test the modules.

This should be the module that you simulate when testing the other modules. Do not modify testbench.

= For example)     if a=3D1, b=3D0 and ei=3D1,   eo will be 1

 

 

Problem = 2: Complete module neq_slice_es (in the homework template) so that it is an explicit

structural description of the 1-bit slice hardware illustrated above. Remember that this module

only handles one bit of and b.

 

Problem = 3: Complete module neq_slice so that it is an implicit structural descriptio= n of the 1-bit

slice hardware illustrated above. Remember that this module only handles = one bit of a and b.

 

Problem = 4: Module nequality is used to compare two four-bit numbers. It has= two four-bit <= span style=3D'font-size:11.0pt;font-family:CMR10;mso-fareast-font-family:"Times = New Roman"; mso-fareast-language:EN-US'>inputs, a and , and a one-bit output eq.

 Complete the module so= that output is 1 iff a and ~b are equal. The module must instantiate four copies of neq_slice,

 fr= om the problem above.

= For example)     if 4 bit  a=3D1111, b=3D0000 or a=3D1= 010, b=3D0101

=             &= nbsp;           &nbs= p;           eq will be 1.

= These are just examples. =

Problem = 5: Draw  figure of a slice just like = the Hw, which will do magnitude comparator for 1 bit

        =           The slice has  6bit input and 3 bit output.=

        =            .a,b : input = :

        =            .eq_in,big_in, smal= l_in: input:    

        =            .eq_out, big_out, small_out: output:

        =             Draw figure of cascade of 3 slices to compare 3 bits number.<= span style=3D'font-size:11.0pt;font-family:CMR10'>

=