//Template for Verilog HW2 Spring 2010
//
//Copy this template and name it "hw2.v".
//

// Problem 0:
// Write down your name and your  account  here
//
// 0.1   Your Name :  #######
// 0.2   Your Account: #######
//
// How much time did you spend to finish this homework?  
    
// 0.3     #############hours #######minutes (fill this at the very end)
//            For example  ## 5 hours 20minutes.

// Problem 1:  Convert the following numbers. (15pts)
//    1.1) Decimal     9      to 8-bit Binary: (2pts)
//     Write your answer here;
//   1.2) Decimal    -9      to 8-bit Binary (2pts)
//     Write your answer here: 
//    1.3) Decimal    9.375  to Binary (as many bits as needed) (3pts)
//     Write your answer here: 
//    1.4) Decimal   -9.375  to IEEE 754 Single Precision (8pts) 
//    (Show in hexadecimal): 
//   Write your answer here: 


//
// Problem 2:(15pts)
//
// Answer:
// Time:    10 11 12  13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
// Output:



// Problem 3(65pts).

//  Complete the module so it can perform the required functionality(65pts).
//  This mini_serial_processing_unit will take bit stream
//   and  process the bit stream by looking the operator.
//   It will stop when the operator value is 1111. 
//  You have to  declare variables and use them.
 module mini_serial_processing_unit(vout,v,ck);
       input ck;
       input v;
      
//You have to declare variables and their sizes here

//
       always @(ck)
       begin
///  Write down your code here
//  For better understanding about the output format,
//  Look at the end of this code where the print format is given. 
///  There will be no penalty for a little bit longer code 
//   as long as your program  produces right answer
       end

 endmodule  //End of your solution for the problem 3.
 
 
 
 
/////     Do not modify this
/////   data memory  for the testbench
/////   you don't have to know these memory and bit_stream_generator module.
/////   these modules  will provide one bit input to the mini_serial_processing_unit module 
/////    at every clock.
module memory();
      reg [4:0] mem[20:0];
      initial
      begin
      mem[0] =  12;     
      mem[1] =  7;         
      mem[2] =  7;     
      mem[3] =  0;            
      mem[4] =  0;   
      mem[5] =  13;              
      mem[6] =  3;
      mem[7] =  12;
      mem[8] =  0;     
      mem[9] =  12;          
      mem[10] = 1;     
      mem[11] = 3;            
      mem[12] = 12;   
      mem[13] = 0;              
      mem[14] = 0;
      mem[15] = 15;
      mem[16] = 0;   
      mem[17] = 15;              
      mem[18] = 15;
      mem[19] = 0;
     
      end
   endmodule
/////   Do not modify this.   
/////     bit_stream_generator module
/////    will provide one bit input to the mini_serial_processing_unit module 
/////    at every clock.
module bit_stream_generator(v,ck);
      input ck;
      output v;
      reg [5:0] local_v, index;
      reg [5:0] cnt;
      reg  v;
     
      memory m();
      initial index = 0;
      initial cnt = 0;
      always @(ck)
      begin
          //#1;
          local_v = m.mem[index];
          v = local_v[3-cnt];
          cnt = cnt+1;
          if(cnt == 4) begin
                        cnt = 0;
                        index = index +1;
                       end 
          if(index ==17) index = 0;
      end
endmodule
//

//////////////////////////////////////////////////////////////////////////////////
////////////////////////////Do not modify this test_all module////////////////////////////////////////////////////
module test_all();
   integer i,j;
    reg ck;
    wire  vs;
    wire [5:0] outout;  
    initial  ck = 0;
    initial begin 
      
             for(i = 1; i<= 40; i = i+ 1) 
              begin
                 #10;
                 ck = ~ck;
              end
    end
    bit_stream_generator b_s_g(vs,ck);   
    mini_serial_processing_unit m_s_p_u(outout,vs,ck);
          
endmodule

//###############YOU MAY USE THE FORMAT BELOW FOR YOUR OUTPUT ####
//## Implement this at your mini_serial_processing_unit
//#####################Print Format##############
//time at  1          input  =      output =
//time at  2          input  =      output =
//   *
//   *
//   *
//
//time at  *   Stop