/// LSU EE 3755  Spring  2007 Verilog_Homework 1- Program template.
 /// Instructions:
  //
  // Copy this to a file( name it  hw1.v) and save on  your
  // class account.   
// Use this file for your solution.  
  //Your entire solution should be  on  this file.
  // Do not rename the modules in this file and be sure to use the filename given above.

////////////////////////////////////////////////////////////////////////////////
/// Problem 0
module hello();
   initial begin
      //display your name and class account.
      // Write your code here.
      // for example
      // if your name is "Clark Kent" and class account is ee375501
      // the exact answer will be: 
      $display("ee375501 Clark Kent\n");//simply change the account number and  name.
   end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 1
module one_bit_and_slice_ex(ab_eq_1,ab_eq_0,a,b);
   input a, b,ab_eq_0;
   output ab_eq_1;
   wire and_ab;
   // your solution goes here  
      

      
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 2
module one_bit_and_slice_im(ab_eq_1,ab_eq_0,a,b);
   input a, b,ab_eq_0;
   output ab_eq_1;
   // your solution goes here  
 
  
  
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 3
module two_one_bit_and_slices (ab_eq_2,a,b,ab_eq_0);
input [1:0]  a, b;
input ab_eq_0;
output ab_eq_2;
wire   ab_eq_1;
   // your solution goes here
   // less than 3 lines.
  

endmodule
////////////////////////////////////////////////////////////////////////////////
//// Problem 4
module one_bit_comparator(AeqB, AgtB, a, b, AeqBin, AgtBin);
input a, b,AeqBin,AgtBin;
output AeqB,AgtB;
reg AeqB,AgtB;

      
     
  
     always  begin
      if(a == b & AeqBin ==1) AeqB = 1; else AeqB = 0;
      
      if(a > b | (a ==b & AgtBin ==1)) AgtB = 1; else AgtB =0;
     #1;
     end     
 
endmodule
//complete this module
module two_bit_comparator(AeqB, AgtB, a, b);
input [1:0]  a, b;
output  AeqB,AgtB;
wire AeqB1,AgtB1;
//Your solution goes here
//less than 3 lines



endmodule
////////////////////////////////////////////////////////////////////////////////
/// Test Bench
/// Do not modify test bench
module test();
   wire  aeqb,agtb;
   reg [1:0]  a, b;
   integer    i;
  two_bit_comparator  com1(aeqb,agtb,a,b);
   initial begin
      for(i=0; i<=15; i=i+1) begin
        a = i[1:0];
        b = i[3:2];
        #10;
     $display("a = %d,b=%d,eq=%d,gt=%d\n",a,b,aeqb,agtb);
     end
      $display("Tests completed.");
  end
endmodule