///#### LSU EE 3755 Fall 2011 Verilog Homework 2- Code template.############# ///#### Instructions: ///#### ///#### Copy this to a file( name it hw2.v) and save on your class account. ///#### Use this file for your solution. ///#### Your entire solution should be on this file. ///#### Do not rename the modules in this file and be sure to use the file name given above. /// //////////////////////////////////////////////////////////////////////////////// /// Problem 0 module hello(); initial begin //#### Display your name and class account. //#### Write your code here. //#### For example //#### If your name is "Clark Kent" and class account is ee375501 //#### The exact answer will be: $display("ee375501 Clark Kent\n");//simply change the account number and name. end endmodule //////////////////////////////////////////////////////////////////////////////// //Problem 1: Convert these numbers to simple float format numbers(10pts). //1-1) 3 //1-2) -1 //Problem 2: What will be value of s_float(six bits)(10pts)? // 2-1) a=011 // b=001 // c=00 // Answer // s_float= // 2-2) a=001 // b=001 // c=01 // Answer // s_float= // 2-3) a =010 // b =001 // c=10 // Answer // s_float = // 2 -4) a= 001 // b=001 // c=11 // Answer // s_float = // Problem 3:Write your code for the SIMPLE_PROCESSING_UNIT(60pts). module simple_processing_unit(s_float,a,b,c); //Complete the module so it can perform the required function. //You have to declare variables and their sizes //You may also code more modules if you need. //Your module should include the code to display the suggested output format. //Don't modify the test bench. endmodule //Problem 4: Convert the following numbers. (15pts) // 4.1) Decimal 5 to 8-bit Binary: (2pts) // Write your answer here; // 4.2) Decimal -5 to 8-bit Binary (2pts) // Write your answer here: // 4.3) Decimal 5.875 to Binary (as many bits as needed) (3pts) // Write your answer here: // 4.4) Decimal -5.875 to IEEE 754 Single Precision (8pts) // (Show in hexadecimal): // Write your answer here: //////////////////////////////////////////////////////////////////////////////// /// Test Bench /// Do not modify test bench module test(); wire[5:0] s_float; reg [2:0] a, b; reg [1:0] c; integer i; simple_processing_unit s_p_u(s_float,a,b,c); initial begin for(i=0; i<=63; i=i+1) begin a = i[2:0]; b = i[5:3]; c = i[3:2]; #10; end $display("Tests completed."); end endmodule