///#### LSU EE 3755 Fall 2011 Verilog Homework 1- Code template.############# ///#### Instructions: ///#### ///#### Copy this to a file( name it hw1.v) and save on your class account. ///#### Use this file for your solution. ///#### Your entire solution should be on this file. ///#### Do not rename the modules in this file and be sure to use the file name given above. /// //////////////////////////////////////////////////////////////////////////////// /// Problem 0 module hello(); initial begin //#### Display your name and class account. //#### Write your code here. //#### For example //#### If your name is "Clark Kent" and class account is ee375501 //#### The exact answer will be: $display("ee375501 Clark Kent\n");//simply change the account number and name. end endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 1 module one_bit_OR_slice_ex(p_out,flag_out,a,b,c,flag_in); input a, b,c,flag_in; output p_out,flag_out; wire and_abc,or_out; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 2 module one_bit_OR_slice_im(p_out,flag_out,a,b,c,flag_in); input a, b,c,flag_in; output p_out,flag_out; wire and_abc,or_out; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 3 module two_one_bit_OR_slices (p_out,flag_out_1,a,b,c,flag_in_0); input [1:0] a, b,c; input flag_in_0; output flag_out_1; output [1:0] p_out; wire flag_out_0; // your solution goes here // less than 3 lines. endmodule //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //// Problem 4 module one_bit_value_checker(P,Flag_out, a, b, Flag_in); input a, b,Flag_in; output Flag_out,P; reg Flag_out,P; always begin Flag_out =0; P = 0; if((a == 1)& (b==0) & (Flag_in == 0)) begin Flag_out = 1; P = 1; end if(Flag_in ==1) begin Flag_out = 1; P=0; end #1; end endmodule //complete this module module three_bit_value_checker(P, a, b); input [2:0] a, b; output[2:0] P; wire Flag_1,Flag_2,Flag_3; //Your solution goes here // 3 lines endmodule //////////////////////////////////////////////////////////////////////////////// /// Test Bench /// Do not modify test bench module test(); wire[2:0] position; reg [2:0] a, b; integer i; three_bit_value_checker com1(position ,a,b); initial begin for(i=0; i<=63; i=i+1) begin a = i[2:0]; b = i[5:3]; #10; $display("a = %b,b=%b,position=%b\n",a,b,position); end $display("Tests completed."); end endmodule