EE3755 Fall 2005 HW3 Due: Oct. 29 Estimated time to finish : 6hours #Name your program hw3.v #Submit hardcopy and leave your program on your account. Problem 0: run the code below ( "memory" and "test") and look at the code. module memory(); reg [3:0] mem [0:15]; integer i; initial begin for(i=0;i<16;i = i+1) mem[i] = i; end endmodule module test(); memory m(); initial begin for(i=0;i<16;i = i+1) $display(" mem[%d] = %b\n",i,m.mem[i]); end endmodule /////////////////////////////////////////////////////////////// Problem 1: Write a program which will read 4bits from the memory at every clock cycle starting at address 0 and go upto address 15 and go back address 0 again. /////////////////////////////// module memory_read_c(v,ck); input ck; output v; //your code comes here (about 10 lines). endmodule /////////////////////////////// Problem 2: Write a program which will read 1bit from the memory at every clock cycle starting at address 0's LSB, next bit,next bit, MSB and go upto address 15 and go back address 0 again (reading one bit at a time). //////////////////////////////// module memory_read_s(v,ck); input ck; output v; //////////////////////// //your solution comes here (about 12 lines) endmodule ////////////////////////////////// Problem 3: Write a program which will read 4bits from the memory at every clock cycle and test if the number of 1s and 0s are equal or not. starting at address 0 and go upto address 15 and go back address 0 again. ////////////////////////////////// // memory_contents same // 0000 0 // 0001 0 // 0010 0 // 0011 1 // xxxx x ////////////// module test_memory_c(same,ck); input ck; output same; reg same; //////// your solution comes here endmodule //////////////// Problem 4: Write a program which will read 1bits from the memory at every clock cycle and test if the number of 1s and 0s are equal or not at every 4 cyles. starting at address 0 and go upto address 15 and go back address 0 again. //////////////////////////////////// module test_memory_s(same,ck); input ck; output same; reg same; /////////// your solution comes here endmodule //////////////// Problem 5. After you finish the problem 1 to the problem 4, Run below test_all module for each of your solution for testing. module test_all(); integer i,j; reg ck; wire [3:0] v1; wire vs; wire same; // memory m(); for the problem 0. // memory_read_c m_r(v1,ck); for the problem 1. // memory_read_s m_r_s(vs,ck); for the problem 2. // test_memory_c t_c(same,ck); for the problem 3. // test_memory_s t_s(same,ck); for the problem 4. initial ck = 0; initial begin for(i = 1; i<= 20; i = i+ 1) begin #1; ck = ~ck; end end always @(ck) begin // $display("problem 1 time = %t , v1 = %b\n",$time,v1); // for the problem 1. // $display("problem 2 time = %t , v1 = %b\n",$time,vs); // for the problem 2. // $display("problem 3 time = %t , same = %b\n", $time,same); //for the problem 3. // $display("problem 3 time = %t , same = %b\n", $time,same); //for the problem 4. end endmodule