//Template for Verilog HW2 Fall  2010
//
//Copy this template and name it "hw2.v".
//


// Problem 0:
// Write down your name and your  account  here
// Your Name :  #######
// Your Account: #######
//
// Problem 1:  Convert the following numbers. (15pts)
//    1.1) Decimal     10      to 8-bit Binary: (2pts)
//     Write your answer here;
//   1.2) Decimal    -10      to 8-bit Binary (2pts)
//     Write your answer here: 
//    1.3) Decimal    10.375  to Binary (as many bits as needed) (3pts)
//     Write your answer here: 
//    1.4) Decimal   -10.375  to IEEE 754 Single Precision (8pts) 
//    (Show in hexadecimal): 
//   Write your answer here: 

// Problem 2(15pts).  Precision in IEEE 754 single. 
// 2.1	Assume you are using IEEE 754 single format for your variables.
//                And you assign values to these two variables.
//                a = 1.23456780
//                b = 1.23456789
//              Is this following sentence true or false? Why?
//               a and b are equal. ( True or False)
//
//
// 2.2         Assume you are using IEEE 754 single format for your variables.
//               And you assign values to these two variables.
//               a =  1.234
//               b =  1.23
//               Is this following sentence true or false? Why?
//               a and b are equal.( True of False)
//
//
//     2.3 Assume you are using IEEE 754 single format for your variable.
//     And you write your code:
//     a = 12345678 + 0.1234567 
//     Does the above code make any sense to you?
//     (why or why not) explain briefly. 
//   
//
//   Problem 3(60pts).
//
//  Complete the module so it can perform the required function.
      
//You have to declare variables and their sizes here
//You may also code more modules if you need.


 module improved_pop(p,a,clk);

   input [31:0] a;
    input        clk;
   output       p;
   reg [5:0]    p1,p2,p3,p4,p21,p22,p31;// for output of each units from fig.2.
// Declare more variables and write your code

   always @( posedge clk )
     begin
//Your code here.

end
endmodule

//Do not modify this testbench.

module test_all();
   integer i;
    reg ck;
    reg [31:0] a;
    wire [5:0] vs;


    
    initial  ck = 0;
    initial begin 
      
             for(i = 1; i<= 200; i = i+ 1) 
              begin
                 #10;
                 ck = ~ck;
                 a = i[31:5]+1;
              end
              end
              improved_pop pop_1(vs,a,ck);
    
endmodule