///#### LSU EE 3755 Fall 2009 Verilog Homework 1- Code template.############# ///#### Instructions: ///#### ///#### Copy this to a file( name it hw1.v) and save on your class account. ///#### Use this file for your solution. ///#### Your entire solution should be on this file. ///#### Do not rename the modules in this file and be sure to use the file name given above. /// //////////////////////////////////////////////////////////////////////////////// /// Problem 0 module hello(); initial begin //#### Display your name and class account. //#### Write your code here. //#### For example //#### If your name is "Clark Kent" and class account is ee375501 //#### The exact answer will be: $display("ee375501 Clark Kent\n");//simply change the account number and name. end endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 1 module one_bit_not_equal_check_with_enable_low_slice_ex(ab_next,ab_prev,enable_low,a,b); input ab_prev,enable_low,a,b; output ab_next; wire xor_ab, not_enable_low, or_abprev_abxor; //##### your solution goes here // endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 2 module one_bit_not_equal_check_with_enable_low_slice_im(ab_next,ab_prev,enable_low,a,b); input ab_prev,enable_low,a,b; output ab_next; //##### your solution goes here // endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 3 module two_one_bit_not_equal_check_with_enable_low_slice_ex (ab_next_1,ab_prev_0,enable_low,a,b); input [1:0] a, b; input ab_prev_0,enable_low; output ab_next_1; wire ab_1; //#### your solution goes here //#### 2 lines. endmodule /// Problem 4 module one_bit_equal_position_detector(P_set_i_1, Position,a,b,P_set_i); input a,b,P_set_i; output P_set_i_1,Position; reg P_set_i_1,Position; always begin P_set_i_1 = 0; Position = 0; if((a == b) & (P_set_i == 0)) begin P_set_i_1 = 1; Position = 1; end #5; if(P_set_i == 1) begin P_set_i_1 = 1; end #5; end endmodule //complete this module module three_bit_equal_position_detector(Position, a, b); input [2:0] a, b; output[2:0] Position; wire [2:0] P_set; //#### Your solution goes here //#### 3 lines endmodule //////////////////////////////////////////////////////////////////////////////// /// Test Bench /// Do not modify test bench module test(); wire[2:0] position; reg [2:0] a, b; integer i; three_bit_equal_position_detector com1(position ,a,b); initial begin for(i=0; i<=63; i=i+1) begin a = i[2:0]; b = i[5:3]; #100; $display("a = %b,b=%b,position=%b\n",a,b,position); end $display("Tests completed."); $finish; end endmodule //########## Hint for problem 4############################################ //## When you run your program, you will see these from the output. //##//// a = 000,.... //##//// ...... //##//// a = 011,b=111,position = 010 //##//// a = 100,b=111,position = 100 //##//// a = ..... //#########################################################################