###### The instruction memory contents at this simulation##
module instruction_memory();
      reg [31:0] mem[0:7];
      initial
      begin
      mem[0] = 32'b00100010000011100001010000000001;
      mem[1] = 32'b10010110010100000010100000000011;     
      mem[2] = 32'b00110110000000111010101011100000;    
      mem[3] = 32'b10111010000000000000000000000000;      
      mem[4] = 32'b00000000000000000000000000000000;     
      mem[5] = 32'b00000000000000000000000000000000;               
      mem[6] = 0;
      mem[7] = 0;
      end
   endmodule
####################################################
####The code template file contains #################
####different instruction memory contents###########
#### so the simulation output will be different#####
#### You may use the above memory contents to check#
#### correctness of your code########################
#####Remember: when you submit your homework,do not
##### modify the contents of instruction memory which is
###### given on the templelate file
---------------------------------------------------------
######This is the result of the simulation#################
######It is better to follow this output format############





LI R[1]  14 
 
LOAD R[2] (000000001)
 
 

SUB R[3] R[1] R[2] 
 
LI R[4] (000000011)

 

STORE R[3] (000000011) 
 
MULT R[5] R[3] R[4]

 

PRINT R[5]  =         33


 

 
THE CONTENTS OF REGISTERS AT THE END OF SIMULATION


 
 REGISTER R[ 0] =          0

 REGISTER R[ 1] =         14

 REGISTER R[ 2] =          3

 REGISTER R[ 3] =         11

 REGISTER R[ 4] =          3
 
 REGISTER R[ 5] =         33

 REGISTER R[ 6] =          0

 REGISTER R[ 7] =          0




 THE CONTENTS OF DATA MEMORY AT THE END OF SIMULATION


 
 MEMORY M[ 0] =          2

 MEMORY M[ 1] =          3

 MEMORY M[ 2] =          1

 MEMORY M[ 3] =         11

 MEMORY M[ 4] =          0

 MEMORY M[ 5] =          0

 MEMORY M[ 6] =          0

 MEMORY M[ 7] =          0