/// LSU EE 3755  Fall  2007 Verilog Homework 2- Program template.
// Instructions:
//
// Copy this to a file( name it  hw2.v) and save on  your  class account.   
// Use this file for your solution.  
    //Your entire solution should be on this file.
    // Do not rename the modules in this file and be sure to use the filename given above.

////////////////////////////////////////////////////////////////////////////////
/// Problem 0
module hello();
   initial begin
      //display your name and class account.
      // Write your code here.
      // for example
      // if your name is "Clark Kent" and class account is ee375501
      // the exact answer will be: 
      $display("ee375501 Clark Kent\n"); //simply change the account number and  name.
   end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 1
//Answer:
//At time    11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
//Output(C):                                                                   


////////////////////////////////////////////////////////////////////////////////
/// Problem 2
module type_one_adder(c,a,b,ck);
   input a, b, ck;
   output c;
   // your solution goes here 
   // less than 30 lines 
 

endmodule
////////////////////////////////////////////////////////////////////////////////

/// Problem 3
//Answer:
//At time    11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
//Output(C):                                                                   


////////////////////////////////////////////////////////////////////////////////
/// Problem 4
module type_two_adder(c,a,b,ck);
   input a, b, ck;
   output c;
   // your solution goes here  
   // less than 35 lines. almost identical to the code for the problem 2. 

endmodule




/// Test Bench
/// Do not modify test bench


module test();
   wire [1:0]   c,c2;
   reg   a,a2, b,b2, ck,ck2;
   integer      i;

   type_one_adder adder1(c,a,b,ck);
   type_two_adder adder2(c2,a2,b2,ck2);
   initial begin
 
      for(i=1; i<=150; i=i+1) begin
        a = i[2:2]*i[3:3];
        b = i[2:2];
        ck = i[0:0];
        #1;
    $display("at the test i= %d ,a = %d,b=%d,c =%d,ck=%d\n",i,a,b,c,ck);
     end
     for(i=1; i<=150; i=i+1) begin
        a2 = i[2:2]*i[3:3];
        b2 = i[2:2];
        ck2 = i[0:0];
        #1;
    $display("at the test i2= %d ,a2 = %d,b2=%d,c2 =%d,ck2=%d\n",i,a2,b2,c2,ck2);
     end
   
     $display("Tests completed.");
 
  end
 
endmodule