// LSU EE 3755 Spring 2008 Verilog_Homework 1- Program template. /// Instructions: // // Copy this to a file( name it hw1.v) and save on your class account. // Use this file for your solution. //Your entire solution should be on this file. // Do not rename the modules in this file and be sure to use the file name given above. //////////////////////////////////////////////////////////////////////////////// /// Problem 0 module hello(); initial begin //display your name and class account. // Write your code here. // for example // if your name is "Clark Kent" and class account is ee375501 // the exact answer will be: $display("ee375501 Clark Kent\n"); //simply change the account number and name. end endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 1 module one_bit_check_first_ones_slice_ex(ab_first_ones,ab_first_ones_next,a,b,ab_pre_first_ones); input a, b, ab_pre_first_ones; output ab_first_ones,ab_first_ones_next; wire and_ab,and_pre_ones; // your solution goes here, 4 lines endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 2 module one_bit_check_first_ones_slice_im(ab_first_ones,ab_first_ones_next,a,b,ab_pre_first_ones); input a, b, ab_pre_first_ones; output ab_first_ones,ab_first_ones_next; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 3 module two_one_bit_check_first_ones_slices (ab_first_ones,ab_first_ones_next,a,b,ab_pre_first_ones); input [1:0] a, b; input ab_pre_first_ones; output[1:0] ab_first_ones; output ab_first_ones_next; wire ab_first_ones_wire; // your solution goes here // 2 lines. endmodule //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //// Problem 4 module three_one_bit_check_first_ones_slices (ab_first_ones,a,b); //you solution goes here //think about the size and value of inputs and outputs input [2:0] a, b; output[2:0] ab_first_ones; wire ab_first_ones_wire_0, ab_first_ones_wire_1, ab_first_ones_wire_2; // your solution goes here // 3 lines. endmodule //////////////////////////////////////////////////////////////////////////////// /// Test Bench /// Do not modify test bench /// You don't have to understand this code. module test(); wire [2:0] ab_first_ones; reg [2:0] a, b; integer i; three_one_bit_check_first_ones_slices slice1(ab_first_ones,a,b); initial begin for(i=0; i<=64; i=i+1) begin a = i[2:0]; b = i[5:3]; #10; $display("a = %b,b=%b,ab_first_ones=%b\n",a,b,ab_first_ones); #1; end $display("Tests completed."); end endmodule