///#### LSU EE 3755  Fall  2008 Verilog_Homework 1- Program template.#############
///#### Instructions:
///####
///#### Copy this to a file( name it  hw1.v) and save on  your class account.   
///#### Use this file for your solution.  
///#### Your entire solution should be on this file.
///#### Do not rename the modules in this file and be sure to use the filename given above.

///
////////////////////////////////////////////////////////////////////////////////
/// Problem 0
module hello();
   initial begin
      //#### Display your name and class account.
      //#### Write your code here.
      //#### For example
      //#### If your name is "Clark Kent" and class account is ee375501
      //#### The exact answer will be: 
      $display("ee375501 Clark Kent\n");//simply change the account number and  name.
   end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 1
module one_bit_or_slice_ex(ab_or_next,ab_or_prev,a,b);
   input  a, b,ab_or_prev;
   output ab_or_next;
   wire   or_ab;
//##### your solution goes here  
//#####   2 lines   
      



      
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 2
module one_bit_or_slice_im(ab_or_next,ab_or_prev,a,b);
   input  a, b,ab_or_prev;
   output ab_or_next;
   wire   or_ab;   
//#### your solution goes here  
//#### 2 lines

 
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 3
module two_one_bit_or_slices (ab_next_2,a,b,ab_prev_0);
input [1:0]  a, b;
input ab_prev_0;
output ab_next_2;
wire   ab_or_1;
//#### your solution goes here
//#### 2 lines.
   

endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 4
module one_bit_priority_and(P_set_i, a, b, Priority_i,P_set_i_1);
input  a,b,P_set_i;
output P_set_i_1,Priority_i;
reg    P_set_i_1, Priority_i;

      
     
  
     always  begin
       P_set_i_1 = 0;
       Priority_i = 0;
      if(a == 1 & b== 1 & P_set_i ==0) begin 
                                  P_set_i_1 =1;
                                  Priority_i =1;
                                  end 
                               
      if(P_set_i ==1) P_set_i_1 = 1;
     #1;
     end     
 
endmodule
//complete this module
module three_bit_priority_and_dector(Priority,  a, b);
input [2:0]  a, b;
output[2:0] Priority;
wire P_set_1,P_set_2,P_set_3;
//#### Your solution goes here
//####  3 lines






endmodule
////////////////////////////////////////////////////////////////////////////////
/// Test Bench
/// Do not modify test bench
module test();
   wire[2:0]  priority;
   reg [2:0]  a, b;
   integer    i;
  three_bit_priority_and_dector  com1(priority ,a,b);
   initial begin
      for(i=0; i<=63; i=i+1) begin
        a = i[2:0];
        b = i[5:3];
        #10;
     $display("a = %b,b=%b,priority=%b\n",a,b,priority);
     end
      $display("Tests completed.");
  end
endmodule
//########## Hint for problem 4############################################
//## When you run your program, you will see these from the output.
//##////  a = 000,....
//##////       ......
//##////  a = 011,b=111,priority=001
//##////  a = 100,b=111,priority=100
//##////  a = .....
//#########################################################################