/// 
/// LSU EE 3755  Fall 2006 Verilog_Homework 1- Program template.
  /// Instructions:
  //
  // Copy this to a file( name it  hw1.v) and 
//save on  your  class account.   
//Use this  file for your solution.  
//Your entire solution should be  on  this file.
  // Do not rename the modules in this file and be sure to use the filename given above.

////////////////////////////////////////////////////////////////////////////////
/// Problem 0
module hello();
   initial begin
      //display your name and class account.
      // Write your code here.
      // for example
      // if your name is "Clark Kent" and class account is ee375501
      // the exact answer will be: 
      $display("ee375501 Clark Kent\n");//simply change the account number and  name.
   end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 1
module half_adder_ex(s,c,a,b);
   input a, b;
   output s,c;
   // your solution goes here  
   //     
     
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 2
module half_adder_im(s,c,a,b);
   input a, b;
   output s,c; 
   // your solution goes here  
 
  
   
   
   
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Problem 3
module full_adder(s,c,a,b,c1);
input  a, b,c1;
   output      s,c;
   wire        s_ha1, c_ha1, c_ha2;
   // your solution goes here



endmodule
/// Problem 4
module two_bit_adder(s,c,a,b,);
input [1:0] a, b;
   output [1:0] s;
output  c;
   wire        c_ha1;
   // your solution goes here
  
   
    
endmodule

////////////////////////////////////////////////////////////////////////////////
/// Test Bench
/// Do not modify test bench
module test();
    wire [2:0] sum1;
   reg [2:0] shadow_sum;
   reg [1:0]  a, b;
   integer    i;
  two_bit_adder  adder1(sum1[1:0],sum1[2],a,b);
   
   task check_sum;
      input [2:0] s;
      input [79:0] name;
 
      if( s != shadow_sum ) begin
         $display("Wrong sum in %s: %d + %d = %d != %d\n",
                  name, a, b, shadow_sum, s);
         $stop;
         end
 
   endtask
 
   initial begin
 
      for(i=0; i<=15; i=i+1) begin
         a = i[1:0];
         b = i[3:2];
         shadow_sum = a + b;
         #10;
         check_sum(sum1,"  twobit_adder");
end
 
      $display("Tests completed.");
 
   end
 
endmodule