Problem 1:  Add Verilog code to the module below.

###################################################

module arith_op(sum,diff,prod,quot,rem,a,b);

input [15:0] a, b;

output [15:0] sum, diff, prod, quot, rem;

assign sum = a+ b;

// Subtraction

assign diff = a- b;

// Multiplication

assign prod =a* b;

// Division

assign quot = a/b;

// Remainder (Modulo)

assign rem =a % b;

endmodule

problem 2: Complete the table.

#################################################

module and_again_again(x1,x2,x3,x4,a,b);

input [2:0] a, b;   // Both a and b are 3 bits.

output [2:0] x1;

output       x2, x3, x4;

// Bitwise AND, but this time operands are 3-bit vectors.

//

assign x1 = a & b;  // ANDs three pairs of bits.

//

// The same thing the hard way:

//

assign x1[0] = a[0] & b[0];

assign x1[1] = a[1] & b[1];

assign x1[2] = a[2] & b[2];

//

//

//  Table:

// a    b    |  a & b

// """"""""""""""""""

// 000  000  | 000

// 000  001  | 000

// 010  111  | 010

// 100  110  | 100

problem 3:   Convert the module below to an explicit structural form.

#####################################################################

module bfa_implicit(sum,cout,a,b,cin);

input a,b,cin;

output sum,cout;

assign sum =

~a & ~b &  cin |

~a &  b & ~cin |

a & ~b & ~cin |

a &  b &  cin;

assign cout = a & b | b & cin | a & cin;

endmodule

module bfa_explicit(sum,cout,a,b,cin);

input a,b,cin;

output sum,cout;

wire   term001, term010, term100,term111;

wire   ab, bc, ac;

wire   na, nb, nc;

or o1(sum,term001,term010,term100,term111);

or o2(cout,ab,bc,ac);

and a1(term001,na,nb,cin);

and a2(term010,na,b,nc);

and a3(term100,a,nb,nc);

and a4(term111,a,b,cin);

not n1(na,a);

not n2(nb,b);

not n3(nc,cin);

and a10(ab,a,b);

and a11(bc,b,cin);

and a12(ac,a,cin);

endmodule

endmodule

problem 4: the module below is Ripple Adder.

#############################################

module ripple_4(sum,cout,a,b);

input [3:0] a, b;

output [3:0] sum;

output       cout;

wire         c0, c1, c2;

bfa_implicit bfa0(sum[0],c0,a[0],b[0],1'b0);

bfa_implicit bfa1(sum[1],c1,a[1],b[1],c0);

bfa_implicit bfa2(sum[2],c2,a[2],b[2],c1);

bfa_implicit bfa3(sum[3],cout,a[3],b[3],c2);

endmodule

a) If a changes at t=5 for ripple_4 module  when does sum change?

// Ans: t = 5.

module ripple_4_d(sum,cout,a,b);

input [3:0] a, b;

output [3:0] sum;

output       cout;

wire         c0, c1, c2;

bfa_implicit_d bfa0(sum[0],c0,a[0],b[0],1'b0);//sum[0] changes at 103,

//c0 changes at 102.

bfa_implicit_d bfa1(sum[1],c1,a[1],b[1],c0);  //sum[1] changes at 105,

//c1 changes at 104.

bfa_implicit_d bfa2(sum[2],c2,a[2],b[2],c1);  //sum[2] changes at 107,

//c2 changes at 106.

bfa_implicit_d bfa3(sum[3],cout,a[3],b[3],c2);//sum[3] changes at 109,

//cout changes at 108.

endmodule

b)

Suppose at t=0 a=0 and b=4'b1111,

If a changes to 1 at t=100 for ripple_4_d module  when does sum stop changing?

// Ans t=109

################################################################

input [7:0] a, b;

output [7:0] sum;

output       overflow;

assign sum = a + b;

wire   sa = a[7];

wire   sb = b[7];

wire   ssum = sum[7];

assign overflow = sa != sb   ? 0 :

sb == ssum ? 0 : 1;

endmodule

problem 6:  Complete the module

// A 5-bit CLA using five cla slice parts.  The generate and propagate

// signals are used to produce the carry  signals.

module cla_5(sum,cout, a,b,cin);

input [4:0] a, b;

input cin;

output [4:0] sum;

output  cout;

wire [4:0]   g, p, carry;

/// Logic for Carry  Signals

assign       carry[0] =  g[0] | cin & p[0];

assign       carry[1] =  g[1]  |

g[0] & p[1] |

cin & p[0] & p[1];

assign       carry[2] =  g[2]  |

g[1] & p[2] |

g[0] & p[1] & p[2]  |

cin & p[0] & p[1] & p[2];

assign       carry[3] = g[3] |

g[2] &p[3] |

g[1] &p[2] & p[3] |

g[0] & p[1] & p[2] &p[3] |

cin  & p[0] & p[1] & p[2] & p[3];

assign       carry[4] = g[4] |

g[3] & p[4] |

g[2] & p[3] & p[4] |

g[1] & p[2] & p[3] & p[4]  |

g[0] & p[1] & p[2] &p[3] & p[4] |

cin  & p[0] & p[1] & p[2] & p[3] & p[4];

assign      sum[0]  = p[0] ^ cin;

assign      sum[1]  = p[1] ^ carry[0];

assign      sum[2]  = p[2] ^ carry[1];

assign      sum[3]  = p[3] ^ carry[2];

assign      sum[4]  = p[4] ^ carry[3];

assign      cout    = carry[4];

cla_slice_part s0(g[0],p[0],a[0],b[0]);

cla_slice_part s1(g[1],p[1],a[1],b[1]);

cla_slice_part s2(g[2],p[2],a[2],b[2]);

cla_slice_part s3(g[3],p[3],a[3],b[3]);

cla_slice_part s4(g[4],p[4],a[4],b[4]);

endmodule

problem 7 : Show the output of the module.

#####################################################

module behavioral_1(x);

output x;

reg [7:0]  x;

initial

// Activity flow starts here at t=0.

// Procedural Code Starts Here

begin

x = 1;

\$display("Hello, x=%d, t=%t",x,\$time);

x = 2;

\$display("Hello, x=%d, t=%t",x,\$time);

x = 3;

\$display("Hello, x=%d, t=%t",x,\$time);

end

endmodule

//Ans.

// Simulator Output

//

// # Hello, x=  1, t=                   0

// # Hello, x=  2, t=                   0

// # Hello, x=  3, t=                   0

module behavioral_2(x);

output x;

reg [7:0]  x;

initial

begin

x = 1;

\$display("Hello, x=%d, t=%t",x,\$time);

#1;

x = 2;

\$display("Hello, x=%d, t=%t",x,\$time);

#1;

x = 3;

\$display("Hello, x=%d, t=%t",x,\$time);

#1;

end

endmodule

// Ans.

// Simulator Output

//

// # Hello, x=  1, t=                   0

// # Hello, x=  2, t=                   1

// # Hello, x=  3, t=                   2

problem 8: Complete the module.

module mux_case(x,select,i0,i1,i2,i3);

input [1:0] select;

input [7:0] i0, i1, i2, i3;

output      x;

reg [7:0]   x;

always @( select or i0 or i1 or i2 or i3 )

begin

case ( select )

0: x = i0;

1: x = i1;

2: x = i2;

3: x = i3;

endcase

end

endmodule

Problem 9 : Complete the module below so that it determines whether its input,

a floating point number in IEEE 754 single format,

is positive, zero, negative, and whether it is an integer.

Output pos is 1 if the input is positive, neg is 1 if it's negative, etc.

module fp_flags(pos,zero,neg,int,single);

input [31:0] single;

output pos, zero, neg, int;

endmodule

//Solution

module fp_flags(pos,zero,neg,int,single);

input [31:0] single;

output pos, zero, neg, int;

reg int;

reg sign;

reg [7:0] exp;

reg [22:0] frac;

reg zero, pos, neg;

reg [5:0] loc;

integer i;

reg found;

always @( single ) begin

sign = single[31];

exp = single[30:23];

frac = single[22:0];

zero = !single[30:0];

pos = !sign && !zero;

neg = sign && !zero;

found = 0;

for(i=0; i<23; i=i+1)if( !found && frac[i] ) begin loc = i; found = 1; end

if( !found ) loc = 23;

int = zero || loc + exp >= 150;

end

endmodule

Problem 10:  The module below is not synthesizable.

module not_synthesizable_sum(sum,a);

input [7:0] a;

output [10:0] sum;

reg [10:0]    sum;

integer       i;

always @( a ) begin

sum = 0;

for(i=0; i<=a; i=i+1) sum = sum + i;

end

endmodule

a) the above module is not synthesizable. Why?(Short answer less than 5 lines)

// loop index is not determined..

b) Make the module synthesizable by modifing some code.

//i< = a --->i < 255

c) What will be the synthesis output after making it synthesizable?

Draw the output as simple as possible.(I don't want you draw 225 copies of the unit).

//  255 copy of (sum = sum + i) ..cascaded..

Problem 11:

Study the BOOTH ALGORITHM.

Problem 12: Convert the following numbers:

Hint (5/8) = 0.625.

Decimal  12 to 8-bit Binary:

//00001100

Decimal -12     to 8-bit Binary:

//00001100

Decimal 12.625  to Binary (as many bits as needed):

//1100.101

Decimal 12.625  to IEEE 754 Single Precision (Show in hexadecimal):

//0x414a0000