November 12,2003

EE3755 EXAM 2:

Do not turn over the page till I say so.

Some problems are very easy so do not spend

Too much time on them.

If you think a problem is difficult, try to solve

The easy ones First.

Name:

SSN:

Problem 01(06pts):

Problem 02(06pts):

Problem 03(08pts):

Problem 04(15pts):

Problem 05(06pts):

Problem 06(06pts):

Problem 07(06pts):

Problem 08(06pts):

Problem 09(06pts):

Problem 10(15pts):

Problem 11(20pts):

Total 100pts

Problem 1: Add Verilog code to the module below for the ripple_carry_counter.

(06pts) ##########################################################

module ripple_carry_counter(q,clk,reset);

output [3:0] q;

input clk, reset;

//######################

//Solution comes here //Hint Instantiation...

T_FF tff0(q[0],clk,reset);

T_FF tff1(q[1],q[0],reset);

T_FF tff2(q[2],q[1],reset);

T_FF tff3(q[3],q[2],reset);

//########################

endmodule

module T_FF(q,clk,reset);

output q;

Input clk,reset;

wire d;

D_FF dffo(q,d,clk,reset);

not n1(d,q); //not is a Verilog-provided primitive. case sensitive

endmodule

//module D_FF with synchronous reset

module D_FF(q,d,clk,reset);

output q;

input d,clk,reset;

reg q;

always @(posedge reset or negedge clk)

if (reset)

q = 1'b0;

else

q = d;

endmodule

problem 2: the module below is a hard way to write a code

Fill the Easy_Way module to do exactly samething. (Hint Vector)

(06pts)##############################################################

module Hard_Way(msb,x3,x2,x1,x0,a3,a2,a1,a0);

output msb;

output x3, x2, x1, x0;

input a3, a2, a1, a0;

assign msb = a3;

assign x3 = a3;

assign x2 = a2;

assign x1 = a1;

assign x0 = a0;

endmodule

//###################

//Solution comes here //Easy Way code is a lot less than Hard_way code.

module Easy_Way(msb,x,a);

output msb;

// Declare x as a 4-bit input, bit 3 is the most-significant bit (MSB).

output [3:0] x;

input [3:0] a;

assign msb = a[3]; // Extract bit 3 from a, which is the MSB.

assign x = a;

endmodule

problem 3: Complete the module

(08pts):###########################################

module three_bit_Booth(prod,ready,multiplicand,multiplier,start,clk);

input [15:0] multiplicand, multiplier;

input start, clk;

output prod;

output ready;

reg [32:0] product;

wire [31:0] prod = product[31:0];

reg [3:0] bit;

wire ready = !bit;

reg d;

initial bit = 0;

wire [16:0] multsx = {multiplicand[15],multiplicand};

always @( posedge clk )

if( ready && start ) begin

bit = 8;

product = { 17'd0, multiplier };

d = 0;

end else if( bit ) begin

//Solutiion comes here

case ( {product[1:0],d} )

3'b001: product[32:16] = product[32:16] + multsx;

3'b010: product[32:16] = ##product[32:16] + multsx;

3'b011: product[32:16] = ##product[32:16] + 2 * multiplicand;

3'b100: product[32:16] = ##product[32:16] - 2 * multiplicand;

3'b101: product[32:16] = ##product[32:16] - multsx;

3'b110: product[32:16] = ##product[32:16] - multsx;

endcase

d = product[1];

product = { product[32], product[32], product[32:2] };

bit = bit - 1;

end

endmodule

Problem 4: the module below is an adder unit.

(15pts):################

module adder(sum,a);

input [7:0] a;

output [10:0] sum;

reg [10:0] sum;

integer i;

always @( a ) begin

sum = 0;

for(i=0; i<4; i=i+1) if( i <= a ) sum = sum + i;

end

endmodule

a) Is the above module synthesizable?

b) What will be the synthesizer output?

Draw the figure.

problem 5: Complete the table.

(06pts)#######################################

module compare(x1,x2,x3,x4,a,b);

input [7:0] a, b; // Both a and b are 8 bits.

output x1, x2, x3, x4;

assign x1 = a > b;

//Solution comes here

// """"""""""""""""""

// 3 1 | 1

// 1 3 | 0

// 1 1 | 0

// x 3 | x

// -1 2 | 1

endmodule

Problem 6: Complete the module.

(06pts)################################################################

// A 5-bit CLA using five cla slice parts. The generate and propagate

// signals are used to produce the carry signals.

module cla_5(sum,cout, a,b,cin);

input [4:0] a, b;

input cin;

output [4:0] sum;

output cout;

wire [4:0] g, p, carry;

/// Logic for Carry Signals

assign carry[0] = g[0] | cin & p[0];

assign carry[1] = g[1] |

g[0] & p[1] |

cin & p[0] & p[1];

assign carry[2] = g[2] |

g[1] & p[2] |

g[0] & p[1] & p[2] |

cin & p[0] & p[1] & p[2];

assign carry[3] = g[3] |

g[2] &p[3] |

g[1] &p[2] & p[3] |

g[0] & p[1] & p[2] &p[3] |

cin & p[0] & p[1] & p[2] & p[3];

assign carry[4] = g[4] |

g[3] & p[4] |

g[2] & p[3] & p[4] |

g[1] & p[2] & p[3] & p[4] |

g[0] & p[1] & p[2] &p[3] & p[4] |

cin & p[0] & p[1] & p[2] & p[3] & p[4];

//Solution comes here

assign sum[0] = p[0] ^ cin;

assign sum[1] = p[1] ^ carry[0];

assign sum[2] = p[2] ^ carry[1];

assign sum[3] = p[3] ^ carry[2];

assign sum[4] = p[4] ^ carry[3];

assign cout = carry[4];

//#####################

cla_slice_part s0(g[0],p[0],a[0],b[0]);

cla_slice_part s1(g[1],p[1],a[1],b[1]);

cla_slice_part s2(g[2],p[2],a[2],b[2]);

cla_slice_part s3(g[3],p[3],a[3],b[3]);

cla_slice_part s4(g[4],p[4],a[4],b[4]);

endmodule

problem 7: Convert the module below to an implicit form.

(06pts)#####################################################################

module bfa_explicit(sum,cout,a,b,cin);

input a,b,cin;

output sum,cout;

wire term001, term010, term100,term111;

wire ab, bc, ac;

wire na, nb, nc;

or o1(sum,term001,term010,term100,term111);

or o2(cout,ab,bc,ac);

and a1(term001,na,nb,cin);

and a2(term010,na,b,nc);

and a3(term100,a,nb,nc);

and a4(term111,a,b,cin);

not n1(na,a);

not n2(nb,b);

not n3(nc,cin);

and a10(ab,a,b);

and a11(bc,b,cin);

and a12(ac,a,cin);

endmodule

//Solution comes here

module bfa_implicit(sum,cout,a,b,cin);

input a,b,cin;

output sum,cout;

input a,b,cin;

output sum,cout;

assign sum =

~a & ~b & cin |

~a & b & ~cin |

a & ~b & ~cin |

a & b & cin;

assign cout = a & b | b & cin | a & cin;

endmodule

Problem 8: The following module my_loop is not working.

(06pts)##############################################

module my_loop(a,b);

input [15:0] b;

output a;

reg [3:0] a;

reg [3:0] i;

integer s;

initial begin

s = 0;

for(i=0; i<16; i=i+1) s = s + a[i];

a = s;

end

endmodule

a) what is wrong with the above module?

Infinity loop.

And only count upto 15 0nes..

b) modify the module as little as possible to make it working.

hint: it has one 16bits input. This is a very easy one. You don’t have to add any more code.

it should count the number of 1s in the input(b).

change [3:0] => [4:0]

problem 9: module not_synthesizable_sum(sum,a);

(06pts)########################

input [7:0] a;

output [10:0] sum;

reg [10:0] sum;

integer i;

initial

always @( a ) begin

sum = 0;

for(i=0; i<=a; i=i+1) #3 sum = sum + i;

end

endmodule:

//Answer the questions

a) the above module is not synthesizable. Why?(Short answer )

initial

delay

undetermined loop index

b) Make the module synthesizable by correcting all mistakes.

Problem 10: Convert the following numbers:

(15pts)

Hint (3/8) = 0.375

a) Decimal 14 to 8-bit Binary:

//00001110

b) Decimal -14 to 8-bit Binary:

// 11110010

c) Decimal 14.375 to Binary (as many bits as needed):

//1110.011

d) Decimal -14.375 to IEEE 754 Single Precision (Show in hexadecimal):

Hint : Hidden one

problem 11: Write a verilog program to add these two special format numbers.

(20pts)

format: Packed BCD

A B C D

bit position: 1111 1100 0000 0000

5432 1098 7654 3210

there are 4 numbers in 16 bits input.

each number is 4 bits long.

when we add two numbers at the same position,

if the result is more than 15 , the result will be set to 15.

This kind of operation is widely used at graphic application.

for example:

input X 0000 0001 0010 0011 1110

input Y 0111 0001 1000 1100 1111

result X+ Y 0111 0010 1010 1111 1111

module packed_bcd(Z,X,Y)

input [15:0] X;

input [15:0] Y;

output [15:0] Z;

//solution comes here

integer I;

reg [4:0] temp1,temp2,temp3,temp4;

always @(X or Y) begin

// Z[3:0] = X[3:0] + Y [3:0] >15 : 15 : X[3:0] + Y [3:0];

// code above is a proper way to do .

// code below is just to show the idea.

temp1 = X [3:0] + Y [3:0];

temp2 = X[7:4] + Y [7:4];

temp3 = X[11:7] +Y[11:7]

temp4 = X[15:12] + Y [15:0];

if (temp1 > 15) temp = 15;

if (temp2 > 15) temp = 15;

if (temp3 > 15) temp = 15;

if (temp4> 15) temp = 15;

Z={temp4[3:0],temp3[3:0],temp2[3:0],temp1[3:0]};

End

Endmodule.