EE3755            Verilog Homework 2  Due: 31 October,2003 
///
 

Solve this problem by modifying a copy of

         http://www.ece.lsu.edu/alex/EE3755/fall03/hw02.v
  
 
 
Problem 0 :
                    copy the homework template into a subdirectory named hw in your class account.
                         The file name should be hw02.v
                         Type your account and name.
 
 
module hello_it_is_me();
   
    $display(“My account, My name\n”); //just type your account and name
 
   
endmodule
 
 
Problem 1
 
 
module find_character_c(character_count,v,character_in);
   input [31:0] v;
   input  [7:0] character_in;
   output [1:0] character_count;
endmodule
 
You are given two inputs.
Input v contains 4 characters.
Input character_in contains ASCII character value.
But you should check only for upper case letter.
You have to count how many times the upper case letter appears in input v.
 
For example) 
Case 1:
When character_in  65  = 01000001(ASCII for “A”);
And v = 01000001 01000001 00000000 00000000
The output character_count should be 2// because “A” appears twice.
 
Case 2:
But When character_in 128 =1000 0000 //this is not a letter.
And v = 1000 0000 1000 0000 1000 0000 0000 0000
The output character_count should be 0 because character_in is not a letter.
//the range of ASCII value for letters are from 65(“A”) to 90(“Z”).
 
Case 3:
When character_in  65  = 01000001(ASCII for “A”);
And v = 00100000101000001000000000000000
Do not interpret this as 0 01000001 01000001 00000000 0000000
 
The output character_count should be 0.
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
/// Problem 2
///
module find_character_s(character_count, character_bit_in,character_in,clk,start);
   input character_bit_in;
   input  [7:0] character_in;
   input clk;
   input start;
   output [4:0] character_count;
   aways @( posedge clk)
      begin
         if(start)
            begin
              //do something here
            end
 
   // Solution goes here.
   
endmodule
 
This is serial version of module find_character_c.
1-bit input character_bit_in will be available at every new clk input.
Input character_in contains ASCII character value.
start follow definition of the class notes.
 
Character_count should be updated at every 8 clk cycles.
Pay attention to the length of character_count.
It is 5 bits now.
 
 
 
But you should check only for upper case letter.
You have to count how many times the upper case letter appears in input v.
 
For example) 
Case 1:
When character_in  65  = 01000001(ASCII for “A”);
And v = 01000001010000010000000000000000
The output character_count should be 1 after certain number of cycles
// because “A” appears.
The output character_count  should be 2 after certain number of cycles
// because second “A”appears.
 
 
Case 2:
But When character_in 128 =1000 0000 //this is not a letter.
And v = 1000 0000 1000 0000 1000 0000 0000 0000
The output character_count should be 0 because character_in is not a letter.
//the range of ASCII value for letters are from 65(“A”) to 90(“Z”).
 
Case 3:
When character_in  65  = 01000001(ASCII for “A”);
And v = 00100000101000001xxxxxxxxxxxxxxxxxxxxxxxxxxx
Do not interpret this as 0 01000001 01000001  
The output character_count should be 0.
//about the start input..
0100000000000000000000000  (start input)
xx01000001xxxxxxxxxxxxxxx  (character_bit_in input)
When character_in = 65,
Character_count should be 1 after certain number of clk cylces.