EE 3755 Homework 1 Due: 20 October 2003

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Solve this problem by modifying a copy of http://www.ece.lsu.edu/alex/EE3755/fall03/hw01.v

Problem 1: Copy the homework template into a subdirectory named hw in your class account. Simulate the welcome module in the homework template.

The logic diagram below is a 1-bit slice of a circuit that is used to determine whether a=~b. One bit of one integer is put on input a and one bit of the other integer is put on input b. (If the number has ten bits then ten slices would be needed.) Ports ei and eo work something like carry in and carry out in a binary full adder. Input ei is logic 1 if the higher bits of the two numbers are not equal. (ahigh=~bhigh). Output eo is logic 1 if ei=1 and a=~b.

An image:

The homework template contains module definitions for solutions to the problems below. It

also contains a testbench, called test, that can be used to test the modules. This should be the module that you simulate when testing the other modules. Do not modify testbench.

For example) if a=1, b=0 and ei=1, eo will be 1

Problem 2: Complete module neq_slice_es (in the homework template) so that it is an explicit

structural description of the 1-bit slice hardware illustrated above. Remember that this module

only handles one bit of a and b.

Problem 3: Complete module neq_slice so that it is an implicit structural description of the 1-bit

slice hardware illustrated above. Remember that this module only handles one bit of a and b.

Problem 4: Module nequality is used to compare two four-bit numbers. It has two four-bit inputs, a and b, and a one-bit output eq. Complete the module so that output eq is 1 iff a and ~b are equal. The module must instantiate four copies of neq_slice, from the problem above.

For example) if 4 bit a=1111, b=0000 or a=1010, b=0101

eq will be 1.

These are just examples.